IP Library › Granted Patent US 12,277,344
Granted Patent B2
US 12,277,344 · App. 18/218,866 · Granted Apr 15, 2025

Flash interface with switching logic

Inventors: Narendra Darapureddy (Vepada, IN); Jacob Albons (Bangalore, IN); Ramanathan Muthiah (Bangalore, IN); Rajesh Neermarga (Bangalore, IN)
Assignee: Sandisk Technologies, Inc.
G06F3/0659G06F3/0619G06F3/0679
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Quick Facts
Patent No.
US 12,277,344
App. No.
18/218,866
Filed
Jul 6, 2023
Granted
Apr 15, 2025
Kind
B2
Art Unit
2137
USPC
711/154
Abstract

There is a large latency and controller bandwidth associated with moving data between dies or between memory devices. The controller includes one or more flash interface modules (FIMs) that are utilized to write data to the memory device and read data from the memory device. Each of the one or more FIMs includes one or more switches. Each switch is utilized to transfer data from a source block to a destination block. Likewise, rather than using a memory external to the FIM to cache the data, the data is stored in a FIM cache and moved from the FIM cache to the relevant physical layer to be programmed to the destination block. Because data is not being transferred to the system memory, the latency and bandwidth associated with relocating data may be decreased.

Claims (80)

1. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller comprises:

a system memory; and

a flash interface module (FIM) coupled to the system memory, wherein the FIM comprises a switch coupled to a physical layer (PHY), and wherein the switch is configured to move data from a die of the memory device via the PHY and to another die of the memory device via the PHY,

wherein the FIM further comprises a cache, and wherein the data is stored in the cache during the moving.

2. The data storage device of claim 1 , wherein the data remains in the FIM during the moving.

3. The data storage device of claim 1 , wherein the controller comprises a plurality of FIMs, wherein the another die is associated with another FIM of the plurality of FIMs, and wherein the data does not pass through the system memory during the moving.

4. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller comprises:

a system memory; and

a flash interface module (FIM) coupled to the system memory, wherein the FIM comprises a switch coupled to a physical layer (PHY), and wherein the switch is configured to move data from a die of the memory device via the PHY and to another die of the memory device via the PHY,

wherein the FIM further comprises a low gear error correction engine, wherein the low gear error correction engine is configured to:

encode data to be programmed to the another die; and

decode encoded data received from the die.

5. The data storage device of claim 1 , wherein the controller is configured to:

enable the switch when the moving occurs.

6. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller comprises:

a system memory; and

a flash interface module (FIM) coupled to the system memory, wherein the FIM comprises a switch coupled to a physical layer (PHY), and wherein the switch is configured to move data from a die of the memory device via the PHY and to another die of the memory device via the PHY,

wherein the switch receives the data from a read first-in first-out (FIFO) queue coupled to the PHY.

7. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller comprises:

a system memory; and

a flash interface module (FIM) coupled to the system memory, wherein the FIM comprises a switch coupled to a physical layer (PHY), and wherein the switch is configured to move data from a die of the memory device via the PHY and to another die of the memory device via the PHY,

wherein the switch sends the data to the PHY via a write FIFO queue.

8. A data storage device, comprising:

a memory device;

a controller coupled to the memory device, wherein the controller comprises:

a system memory;

a plurality of flash interface modules (FIMs) coupled to the system memory and the memory device, wherein each of the plurality of FIMs comprises one or more switches, and wherein the controller is configured to:

transfer data between dies associated with a same FIM without using the system memory; and

transfer data between dies associated with different FIMs without using the system memory.

9. The data storage device of claim 8 , wherein transferring the data between the dies associated with the same FIM without using the system memory further comprises:

sensing the data from a source die to a latch of the source die;

transferring the data from the latch of the source die to a read first-in first-out (FIFO) queue; and

storing the data in a cache of the same FIM from the read FIFO queue.

10. The data storage device of claim 9 , wherein transferring the data between the dies associated with the same FIM without using the system memory further comprises:

selecting the cache of the same FIM as source data to program to a destination die associated with the same FIM;

transferring the data to a write FIFO queue via a switch of the same FIM, wherein the switch is associated with the destination die;

transferring the data from the write FIFO queue to a latch of the destination die; and

programming the data to the destination die from the latch of the destination die.

11. The data storage device of claim 8 , wherein transferring the data between the dies associated with the different FIMs without using the system memory further comprises:

sensing the data from a source die to a latch of the source die associated with a source FIM;

transferring the data from the latch of the source die to a read FIFO queue of the source FIM; and

storing the data in a cache of the source FIM from the read FIFO queue.

12. The data storage device of claim 11 , wherein transferring the data between the dies associated with the different FIMs without using the system memory further comprises:

selecting the cache of the source FIM as source data to program to a destination die associated with a destination FIM;

transferring the data to a write FIFO queue of the destination FIM associated with the destination die via a switch of the destination FIM, wherein the switch is associated with the destination die;

transferring the data from the write FIFO queue to a latch of the destination die; and

programming the data to the destination die from the latch of the destination die.

13. The data storage device of claim 8 , wherein the controller is further configured to:

determine whether a source FIM and a destination FIM associated with a relocation request is for the same FIM or the different FIMs.

14. The data storage device of claim 13 , wherein the controller is further configured to:

enable a switch of the same FIM when the source FIM and the destination FIM associated with the relocation request is for the same FIM, wherein transferring data between the dies associated with the same FIM without using the system memory is responsive to enabling the switch of the same FIM.

15. The data storage device of claim 13 , wherein the controller is further configured to:

enable a switch of the different FIM when the source FIM and the destination FIM associated with the relocation request are for the different FIMs, wherein transferring data between the dies associated with the different FIMs without using the system memory is responsive to enabling the switch of the different FIM.

16. A data storage device, comprising:

means for storing data; and

a controller coupled to the means for storing data, wherein the controller comprises:

a system memory; and

one or more flash interface modules (FIMs) coupled to the system memory and the means for storing data, wherein the FIM further comprises a cache, and wherein the one or more FIMs are configured to:

move data from a source location of the means for storing data to a destination location of the means for storing data without using the system memory, wherein the data is stored in the cache during the moving.

17. The data storage device of claim 16 , wherein the system memory is volatile memory.

18. The data storage device of claim 16 , wherein the one or more FIMs comprises one or more switches, wherein each of the one or more switches are associated with a location of the means for storing data.

19. A data storage device, comprising:

means for storing data; and

a controller coupled to the means for storing data, wherein the controller comprises:

a system memory; and

one or more flash interface modules (FIMs) coupled to the system memory and the means for storing data, wherein the one or more FIMs are configured to:

move data from a source location of the means for storing data to a destination location of the means for storing data without using the system memory, wherein moving data from the source location to the destination location comprises:

storing the data from the source location in a source cache, wherein the source cache is disposed in a source FIM associated with the source location; and

enabling a switch of the one or more switches of a destination FIM, wherein the destination FIM is associated with the destination location, and wherein:

the source FIM and the destination FIM are the same; or

the source FIM and the destination FIM are different.

20. The data storage device of claim 19 , wherein the one or more FIMs each comprise a write first in first out (FIFO) queue and a read FIFO queue.

Assignments (9)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2023
From: PATHIRAKANI, GANESH KUMAR; NAYAK, DATTATREYA; RAMADOSS, VENKATESH; NIMMAGADDA, TARUN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 064197/0222 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2023
From: DARAPUREDDY, NARENDRA; ALBONS, JACOB; MUTHIAH, RAMANATHAN; NEERMARGA, RAJESH
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 064199/0278 →
Continuity (2)
Provisional Application 63455395 · Mar 29, 2023
Related Publication 20240329880A1 · Oct 3, 2024
References Cited (15)
US 9152496B2 · Kanade et al. · 2015 [cited by applicant]
US 9158621B2 · Sharon et al. · 2015 [cited by applicant]
US 10534729B1 · Maidee et al. · 2020 [cited by applicant]
US 10642513B2 · Marcu et al. · 2020 [cited by applicant]
US 10971215B1 · Yang et al. · 2021 [cited by applicant]
US 11113222B2 · Law · 2021 [cited by applicant]
US 20200142849A1 · Law · 2020 [cited by examiner]
US 20210294739A1 · Oh · 2021 [cited by examiner]
US 20220028475A1 · Sharon et al. · 2022 [cited by applicant]
US 20220058140A1 · Zimmerman et al. · 2022 [cited by applicant]
US 20220121375A1 · Kim · 2022 [cited by examiner]
US 20220308769A1 · Muthiah et al. · 2022 [cited by applicant]
US 20240028249A1 · Confalonieri · 2024 [cited by examiner]
US 20240069721A1 · Sankaranarayanan · 2024 [cited by examiner]
US 20240070065A1 · Hoang · 2024 [cited by examiner]