Controller and memory system
A memory system includes a first memory device including a plurality of first physical blocks; a second memory device including a plurality of second physical blocks; a first core suitable for managing a plurality of first super blocks that store data associated with a first logical address, the plurality of first super blocks being mapped to the plurality of first physical blocks; a second core suitable for managing a plurality of second super blocks that store data associated with a second logical address, the plurality of second super blocks being mapped to the plurality of second physical blocks; a global wear-leveling manager suitable for changing mapping between the first physical blocks, which are mapped to one among the first super blocks, and the second physical blocks, which are mapped to one among the second super blocks based on degrees of wear of the first and second super blocks.
1. A memory system comprising:
a first memory device including a plurality of first physical blocks;
a second memory device including a plurality of second physical blocks;
a first core suitable for managing a plurality of first super blocks that store data associated with a first logical address, the plurality of first super blocks being mapped to the plurality of first physical blocks;
a second core suitable for managing a plurality of second super blocks that store data associated with a second logical address, the plurality of second super blocks being mapped to the plurality of second physical blocks;
a global wear-leveling manager suitable for changing address mapping from a first physical block of the first physical blocks, which are mapped to one among the first super blocks by the first core, to a second physical block of the second physical blocks, which are mapped to one among the second super blocks by the second core, or vice versa, based on degrees of wear of the first and second super blocks;
a host interface suitable for sorting logical addresses, which are received from a host, into the first and second logical addresses, providing the first core with the first logical address, and providing the second core with the second logical address;
a global virtual flash layer (VFL) that performs mapping a first virtual address and a second virtual address to physical addresses associated with the first physical block and the second physical block, wherein the first core drives a first local flash translation layer (FTL) that performs mapping between the first virtual address, which is an address of the first super blocks, and the first logical address, and the second core drives a second local FTL that performs mapping between the second virtual address, which is an address of the second super blocks, and the second logical address;
a first hardware accelerator suitable for queuing a command provided from the first and second local FTLs to the global VFL; and
a second hardware accelerator suitable for scheduling commands provided from the first core and the second core to the first memory device and the second memory device.
2. The memory system of claim 1 , wherein the degrees of wear of the super blocks are determined by erase counts of the physical blocks mapped to the super blocks.
3. The memory system of claim 2 ,
wherein the global wear-leveling manager changes the mapping of the first physical blocks and the second physical blocks between the corresponding first and second super blocks when
the corresponding first super block is a global maximum super block,
the corresponding second super block is a global minimum super block and
a difference between the degrees of wear of the corresponding first and second super blocks is equal to or greater than a threshold value,
wherein the global maximum super block has the highest degree of wear among all of the first and second super blocks, and
wherein the global minimum super block has the lowest degree of wear among all of the first and second super blocks.
4. The memory system of claim 3 , wherein the global wear-leveling manager restores, when the difference between the degrees of wear of the corresponding first and second super blocks become less than the threshold value, the changed mapping to the mapping before the mapping was changed.
5. The memory system of claim 1 ,
wherein the first core drives a first local FTL that performs mapping between the first logical address and a first virtual address associated with the first super blocks, and drives a first local VFL that performs mapping between the first virtual address and a physical address, and
wherein the second core drives a second local FTL that performs mapping between the second logical address and a second virtual address associated with the second super blocks, and drives a second local VFL that performs mapping between the second virtual address and a physical address.
6. The memory system of claim 1 ,
wherein the first core performs a local wear-leveling operation of moving data between the first super blocks based on the degrees of wear of the first super blocks, and
wherein the second core performs a local wear-leveling operation of moving data between the second super blocks based on the degrees of wear of the second super blocks.
7. A controller that controls a first memory device and a second memory device, the controller comprising:
a first core suitable for managing a plurality of first super blocks that store data associated with a first logical address, the plurality of first super blocks being mapped to a plurality of first physical blocks included in the first memory device;
a second core suitable for managing a plurality of second super blocks that store data associated with a second logical address, the plurality of second super blocks being mapped to a plurality of second physical blocks included in the second memory device;
a global wear-leveling manager suitable for swapping a first physical block of the first physical blocks, which are mapped to one among the first super blocks by the first core, for a second physical block of the second physical blocks, which are mapped to one among the second super blocks by the second core, or vice versa, based on degrees of wear of the first and second super blocks;
a host interface suitable for sorting logical addresses, which are received from a host, into the first logical address and the second logical address, providing the first core with the first logical address, and providing the second core with the second logical address;
a global virtual flash layer (VFL) that performs mapping a first virtual address and a second virtual address to physical addresses associated with the first physical block and the second physical block, wherein the first core drives a first local flash translation layer (FTL) that performs mapping between the first virtual address, which is an address of the first super blocks, and the first logical address, and the second core drives a second local FTL that performs mapping between the second virtual address, which is an address of the second super blocks, and the second logical address;
a first hardware accelerator suitable for queuing a command provided from the first and second local FTLs to the global VFL; and
a second hardware accelerator suitable for scheduling commands provided from the first core and the second core to the first memory device and the second memory device.
8. The controller of claim 7 , wherein the degrees of wear of the super blocks are determined by erase counts of the physical blocks mapped to the super blocks.
9. The controller of claim 8 ,
wherein the global wear-leveling manager changes mapping of the first physical blocks and the second physical blocks between the corresponding first and second super blocks when the corresponding first super blocks is a global maximum super block,
the corresponding second super block is a global minimum super block and
a difference between the degrees of wear of the corresponding first and second super blocks is equal to or greater than a threshold value,
wherein the global maximum super block has the highest degree of wear among all of the first and second super blocks, and
wherein the global minimum super block has the lowest degree of wear among all of the first and second super blocks.
10. The controller of claim 9 , wherein the global wear-leveling manager restores, when the difference between the degrees of wear of the corresponding first and second super blocks become less than the threshold value, the changed mapping to the mapping before the mapping was changed.
11. The controller of claim 7 ,
wherein the first core drives a first local FTL that performs mapping between the first logical address and a first virtual address associated with the first super blocks, and drives a first local VFL that performs mapping between the first virtual address and a physical address, and
wherein the second core drives a second local FTL that performs mapping between the second logical address and a second virtual address associated with the second super blocks, and drives a second local VFL that performs mapping between the second virtual address and a physical address.
12. The controller of claim 7 ,
wherein the first core performs a local wear-leveling operation of moving data between the first super blocks based on the degrees of wear of the first super blocks, and
wherein the second core performs a local wear-leveling operation of moving data between the second super blocks based on the degrees of wear of the second super blocks.
13. A memory system comprising:
a plurality of memory devices including first and second groups of memory units, the first and second groups being exclusively and individually used by a first core and a second core;
the first core and the second core individually allocating the first and second groups for storing data;
a global wear-leveling manager suitable for exchanging, based on degrees of wear of the respective memory units, a first memory unit of the first group allocated by the first core with a second memory unit of the second group allocated by the second core, or vice versa;
a global virtual flash layer (VFL) that performs mapping a first virtual address and a second virtual address to physical addresses associated with a first physical memory unit in the first group and a second physical memory unit in the second group, wherein the first core drives a first local flash translation layer (FTL) that performs mapping between the first virtual address, which is an address of first super memory units, and the first logical address, and the second core drives a second local FTL that performs mapping between the second virtual address, which is an address of second super memory units, and the second logical address;
a first hardware accelerator suitable for queuing a command provided from the first local FTL and the second local FTL to the global VFL; and
a second hardware accelerator suitable for scheduling commands provided from the first core and the second core to the first memory device and the second memory device.
14. The memory system according to claim 13 , wherein the global wear-leveling manager changes mapping between a logical address associated with the data and a physical address associated with the first memory unit or the second memory unit to exchange the first memory unit and the second memory unit.