Method and apparatus for inter-die data transfer

1. An inter-die data transfer system, comprising:

a receiver circuit in a receiver die, wherein the receiver circuit includes:

a safe sample selection circuit configured to:

receive, through a bus from a sender circuit in a sender die, a plurality of training data signals corresponding to a plurality of bits of the bus respectively;

determine a safe sample selection signal based on a first training data signal corresponding to a first bit of the bus;

receive, through the bus, a plurality of user data input signals from the sender circuit corresponding to the plurality of bits of the bus respectively; and

select, using the safe sample selection signal, a user data safe sample from a plurality of user data samples for a first user data input signal associated with the first bit of the bus;

a latency adjustment circuit configured to:

determine a latency adjustment selection signal associated with the first bit of the bus based on the plurality of training data signals; and

perform latency adjustment to the user data safe sample to generate a first user data output signal using the latency adjustment selection signal.

2. The inter-die data transfer system of claim 1 , wherein the safe sample selection circuit further includes:

a sampling circuit configured to:

sample a first training data symbol of the first training data signal at a plurality of sampling times to generate a plurality of training data samples;

wherein the safe sample selection signal is determined using the plurality of training data samples.

3. The inter-die data transfer system of claim 2 , wherein the plurality of sampling times includes a first sampling time and a second sampling time adjacent to the first sampling time, and

wherein a first time period between the first and second sampling times is determined based on a metastability limitation of the plurality of training data samples.

4. The inter-die data transfer system of claim 3 , wherein at most one of the plurality of training data samples is metastable.

5. The inter-die data transfer system of claim 3 , wherein the sampling circuit includes a first register configured to generate a first training data sample at the first sampling time, and

wherein the first time period is greater than a combined time of a setup time of the first register and a hold time of the first register.

6. The inter-die data transfer system of claim 2 , wherein the safe sample selection circuit includes:

a stabilizer circuit configured to stabilize the plurality of training data samples to generate a plurality of stabilized training data samples;

wherein the safe sample selection signal is determined using the plurality of stabilized training data samples.

7. The inter-die data transfer system of claim 6 , wherein the stabilizer circuit includes:

a plurality of delay elements connected in serial to obtain valid binary values of the plurality of training data samples.

8. The inter-die data transfer system of claim 1 , wherein the safe sample selection signal is determined based on the first training data signal having a first pattern, and

wherein the latency adjustment selection signal is determined based on the first training data signal having a second pattern.

9. The inter-die data transfer system of claim 8 , wherein the first pattern toggles once every clock cycle; and

wherein the second pattern toggles once every two or more clock cycles.

10. The inter-die data transfer system of claim 1 , wherein the latency adjustment circuit is configured to:

receive a first training data safe sample for a first training data symbol of the first training data signal;

receive a second training data safe sample for a second training data symbol of a second training data signal corresponding to a second bit of the bus; and

determine the latency adjustment selection signal by detecting a latency difference between the first training data safe sample and the second training data safe sample.

11. A method, comprising:

receiving, by a receiver circuit in a receiver die through a bus from a sender circuit in a sender die, a plurality of training data signals corresponding to a plurality of bits of the bus respectively;

determining, by a safe sample selection circuit of the receiver circuit, a safe sample selection signal based on a first training data signal corresponding to a first bit of the bus;

determining a latency adjustment selection signal associated with the first bit of the bus based on the plurality of training data signals;

receiving, by the receiver circuit through the bus from the sender circuit, a plurality of user data input signals corresponding to the plurality of bits of the bus respectively;

selecting, using the safe sample selection signal, a user data safe sample from a plurality of user data samples for a first user data input signal associated with the first bit of the bus; and

performing latency adjustment to the user data safe sample to generate a first user data output signal using the latency adjustment selection signal.

12. The method of claim 11 , wherein the determining the safe sample selection signal further includes:

sampling a first training data symbol of the first training data signal at a plurality of sampling times to generate a plurality of training data samples;

wherein the safe sample selection signal is determined using the plurality of training data samples.

13. The method of claim 12 , wherein the plurality of sampling times includes a first sampling time and a second sampling time adjacent to the first sampling time, and

wherein a first time period between the first and second sampling times is determined based on based on a metastability limitation of the plurality of training data samples.

14. The method of claim 13 , wherein at most one of the plurality of training data samples is metastable.

15. The method of claim 13 , wherein a first register is configured to generate a first training data sample at the first sampling time, and

wherein the first time period is greater than a combined time of a setup time of the first register and a hold time of the first register.

16. The method of claim 12 , wherein the determining the safe sample selection signal further includes:

stabilizing the plurality of training data samples to generate a plurality of stabilized training data samples;

wherein the safe sample selection signal is determined using the plurality of stabilized training data samples.

17. The method of claim 16 , wherein the stabilizing the plurality of training data samples includes:

obtaining valid binary values of the plurality of training data samples using a plurality of delay elements connected in serial.

18. The method of claim 11 , wherein the safe sample selection signal is determined based on the first training data signal having a first pattern, and

wherein the latency adjustment selection signal is determined based on the first training data signal having a second pattern.

19. The method of claim 18 , wherein the first pattern toggles once every clock cycle; and

wherein the second pattern toggles once every two or more clock cycles.

20. The method of claim 11 , wherein the determining the latency adjustment selection signal includes:

receiving a first training data safe sample for a first training data symbol of the first training data signal;

receiving a second training data safe sample for a second training data symbol of a second training data signal corresponding to a second bit of the bus; and

determining the latency adjustment selection signal by detecting a latency difference between the first training data safe sample and the second training data safe sample.