Semi and cached TLP coalescing
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, wherein the command comprises a plurality of logical block addresses (LBAs), determine that one or more LBAs of the plurality of LBAs are not aligned to a transfer layer packet (TLP) boundary, determine whether the one or more LBAs that are not aligned to a TLP boundary has a head that is unaligned that matches a previously stored tail that is unaligned, and merge and transfer the head that is unaligned with a previously stored tail that is unaligned when the head that is unaligned matches the previously stored tail that is unaligned.
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
receive a command, wherein the command comprises a plurality of logical block addresses (LBAs);
determine that one or more LBAs of the plurality of LBAs are not aligned to a transfer layer packet (TLP) boundary;
determine whether the one or more LBAs that are not aligned to a TLP boundary has a head that is unaligned that matches a previously stored tail that is unaligned; and
merge and transfer the head that is unaligned with a previously stored tail that is unaligned when the head that is unaligned matches the previously stored tail that is unaligned.
2. The data storage device of claim 1 , wherein the controller is further configured to:
determine if a head slot is occupied when the head that is unaligned does not match the previously stored tail that is unaligned; and
store the head that is unaligned in the head slot when the head slot is unoccupied.
3. The data storage device of claim 2 , wherein the controller is further configured to either:
send the head that is unaligned to an interface of the controller when the head slot is occupied; or
transfer a stored head in the head slot to the interface when the head slot is occupied and store the head that is unaligned in the head slot after the transferring.
4. The data storage device of claim 1 , wherein the merging further comprises erasing the previously stored tail that is unaligned.
5. The data storage device of claim 1 , wherein the transferring occurs in the TLP size.
6. The data storage device of claim 1 , wherein the controller is further configured to:
determine whether the one or more LBAs that are not aligned to a TLP boundary has a tail that is unaligned that matches a previously stored head that is unaligned; and
merge and transfer the tail that is unaligned with a previously stored head that is unaligned when the tail is unaligned that matches the previously stored head that is unaligned.
7. The data storage device of claim 6 , wherein the controller is further configured to:
determine if a tail slot is occupied when the tail that is unaligned does not match the previously stored head that is unaligned; and
store the tail that is unaligned in the tail slot when the tail slot is unoccupied.
8. The data storage device of claim 7 , wherein the controller is further configured to either:
send the tail that is unaligned to an interface of the controller when the tail slot is occupied; or
transfer a stored tail in the tail slot to the interface when the tail slot is occupied and store the tail that is unaligned in the tail slot after the transferring.
9. The data storage device of claim 6 , wherein the merging further comprises erasing the previously stored head that is unaligned.
10. The data storage device of claim 1 , further comprising a merging buffer and a timer.
11. The data storage device of claim 10 , wherein the merging buffer includes a plurality of head slots and a plurality of tail slots.
12. The data storage device of claim 11 , wherein the controller is further configured to either:
use all of the plurality of head slots to store unaligned heads and the plurality of tail slots to store unaligned tails; or
assign a portion of the plurality of head slots and a portion of the plurality of tail slots to a flash interface module (FIM) channel of two or more FIM channels.
13. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
receive a plurality of logical block addresses (LBAs);
determine that at least one LBA of a flash interface module (FIM) is unaligned to a transfer layer packet (TLP) size;
store either a head or a tail of the at least one LBA in a merging buffer, wherein the head or the tail corresponds with an unaligned portion of the at least one LBA;
either:
merge the head with another unaligned tail stored in the merging buffer, wherein the another unaligned tail corresponds to a different LBA; or
merge the tail with another unaligned head stored in the merging buffer, wherein the another unaligned head corresponds to a different LBA; and
program the merged LBA to a host device.
14. The data storage device of claim 13 , wherein the another unaligned tail and/or the another unaligned head is a previously merged unaligned head or a previously merged unaligned tail.
15. The data storage device of claim 13 , wherein the plurality of LBAs are received consecutively and processed non-consecutively.
16. The data storage device of claim 13 , wherein the controller is further configured to store the head in a head slot when there is not another unaligned tail stored in the merging buffer that matches the head or store the tail in a tail slot when there is not another unaligned head stored in the merging buffer that matches the tail.
17. The data storage device of claim 16 , wherein the controller is configured to evict the stored head and/or the stored tail when a respective time threshold is reached or exceeded, wherein the respective time threshold is based on either a random workload, a sequential workload, or a combination of the random workload and the sequential workload.
18. The data storage device of claim 17 , wherein the evicting comprises programming the stored head and/or the stored tail to the memory device as an unaligned LBA.
19. A data storage device, comprising:
memory means; and
a controller coupled to the memory means, wherein the controller is configured to:
receive one or more unaligned logical block address (LBAs);
determine that a head of a received unaligned LBA is unaligned with a transfer layer packet (TLP) boundary or that a tail of the received unaligned LBA is unaligned with the TLP boundary;
store the head or the tail in a merging buffer;
determine if there is another tail in the merging buffer that matches the head or if there is another head in the merging buffer that matches the tail;
merge the another tail and the head when the another tail matches the head or merge the another head and the tail when the another head matches tail; and
program the merged another head or the merged another tail to a host device.
20. The data storage device of claim 19 , wherein the controller is further configured to maintain the merging buffer in a full-cached mode or a semi-cached mode.