Programming to a correctable amount of errors
View Patent ↗Apparatuses, systems, methods, and computer program products are disclosed for distributed program operation. One apparatus includes a non-volatile storage controller that identifies a threshold number of bit flips that can be corrected in an amount of read data and a memory die comprising a plurality of non-volatile memory cells. Here, the memory die receives the threshold number of bit flips from the non-volatile storage controller, programs data to a set of the non-volatile memory cells over a first number of program loop cycles, and programs the data to the set of non-volatile memory cells over an additional number of program loop cycles in response to the amount of bit flips in the set of memory cells exceeding the threshold number of bit flips.
1. An apparatus comprising:
a non-volatile storage controller that identifies a threshold number of bit flips that can be corrected in an amount of read data; and
a memory die comprising a plurality of non-volatile memory cells, wherein the memory die:
receives the threshold number of bit flips from the non-volatile storage controller;
programs data to a set of the non-volatile memory cells over a first number of program loop cycles; and
programs the data to the set of non-volatile memory cells over an additional number of program loop cycles in response to the amount of bit flips in the set of memory cells exceeding the threshold number of bit flips.
2. The apparatus of claim 1 , wherein the non-volatile storage controller sends a program command to the memory die, wherein memory die further:
tracks the accumulative number of program loop cycles used to program the set of non-volatile memory cells;
indicates completion of the program command in response to the amount of bit flips in the set of memory cells not exceeding the threshold number of bit flips; and
reports the accumulative number to the non-volatile storage controller.
3. The apparatus of claim 2 , wherein the non-volatile storage controller marks the set of non-volatile memory cells as partially programmed in response to the memory die indicating completion of the program command.
4. The apparatus of claim 1 , wherein the memory die analyzes whether an amount of bit flips in the set of the non-volatile memory cells exceeds the threshold number of bit flips in response to performing the first number of program loop cycles.
5. The apparatus of claim 1 , wherein the non-volatile storage controller further indicates to the memory die a number of program loop cycles to perform without verifying a programmed voltage level, wherein the first number of program loop cycles is based on the number of program loop cycles to perform without verifying a programmed voltage level.
6. The apparatus of claim 5 , wherein the non-volatile storage controller calculates the number of program loop cycles to perform without verifying a programmed voltage level based on an accumulative number of program loop cycles used to program another set of non-volatile memory cells of the memory die.
7. The apparatus of claim 1 , wherein the memory die includes a read data buffer, wherein determining whether the amount of bit flips in the set of the non-volatile memory cells exceeds the threshold number of bit flips comprises the memory die reading data from the set of non-volatile memory cells into the read data buffer and comparing the read data buffer to source data received from the non-volatile storage controller.
8. A method comprising:
receiving, at a memory die and from a non-volatile storage controller, a threshold number of bit errors that are correctable by the non-volatile storage controller;
programming, by the memory die, a set of non-volatile memory cells with a number of first program pulses;
reading data stored to the set of non-volatile memory cells after the number of first program pulses;
analyzing, by the memory die, whether a read number of bit errors exceeds the threshold number of bit errors; and
notifying the non-volatile storage controller that the set of non-volatile memory is successfully programmed based on the result of the analysis.
9. The method of claim 8 , further comprising:
programming the set of non-volatile memory with an additional number of program pulses in response to the read number of bit errors exceeding the threshold number of bit errors;
reading data stored to the set of non-volatile memory cells after each additional program pulse; and
re-analyzing whether a read number of bit errors exceeds the threshold number of bit errors after each read.
10. The method of claim 9 , further comprising receiving a maximum number of program pulses from the non-volatile storage controller, and reporting an error condition to the non-volatile storage controller in response to the additional number of program pulses reaching the maximum number of program pulses.
11. The method of claim 9 , further comprising notifying the non-volatile storage controller of the total number of program pulses performed.
12. The method of claim 8 , wherein notifying the non-volatile storage controller that the set of non-volatile memory cells is successfully programmed comprises notifying the non-volatile storage controller that the set of non-volatile memory is successfully programmed in response to the read number of bit errors not exceeding the threshold number of bit errors.
13. The method of claim 8 , wherein notifying the non-volatile storage controller that the set of non-volatile memory cells is successfully programmed comprises indicating that the set of non-volatile memory cells is in a partially programmed state.
14. The method of claim 13 , further comprising receiving a command from the non-volatile storage controller to program the set of non-volatile memory cells to a fully programmed state, and programming the set of non-volatile memory cells with a number of second program pulses in response to the command.
15. The method of claim 14 , further comprising receiving the number of second program pulses from the non-volatile storage controller.
16. The method of claim 14 , further comprising reading data stored to the set of non-volatile memory cells after each second program pulse, wherein programming the set of non-volatile memory cells with a number of second program pulses comprises programming the set of non-volatile memory cells until the read data reaches a set of program verify thresholds.
17. A memory die apparatus comprising:
means for receiving, from a storage controller, a correctable number of bit errors;
means for receiving, from the storage controller, source data to be programmed to a set of memory cells;
means for programming the set of memory cells;
means for reading data stored to the set after a program loop cycle;
means for analyzing whether an amount of bit errors in data read from the set is correctable based on the correctable number of bit errors; and
means for signaling, to the storage controller, completion of a program command based on the analysis.
18. The apparatus of claim 17 , wherein the means for programming the set of memory cells programs the set using an additional number of program loop cycles in response to the amount of bit errors not being correctable.
19. The apparatus of claim 18 , further comprising means for receiving a maximum number of program loop cycles from the non-volatile storage controller, wherein programming the set using an additional number of program loop cycles comprises applying up to the maximum number of program loop cycles.
20. The apparatus of claim 17 , further comprising means for notifying the storage controller of a number of program pulses performed until the amount of bit errors in the data becomes correctable.