Methods and systems to reduce SSD IO latency
View Patent ↗Techniques for reducing Solid State Device Input/Output latency are disclosed. In some embodiments, the techniques may be realized as a method for reducing Solid State Device Input/Output latency comprising receiving a write request at a Solid State Device, monitoring a plurality flash memory channels of the Solid State Device to identify Input/Output requests, evaluating, using load balancing circuitry, identified Input/Output requests to determine a load of one or more of the plurality of flash memory channels, and assigning a destination flash memory channel out of the plurality of flash memory channels to the write request based on the determined load.
1. A method for reducing Solid State Device Input/Output latency comprising:
receiving a write request at a Solid State Device;
monitoring a plurality of flash memory channels of the Solid State Device to identify Input/Output requests wherein the monitoring is at a physical channel;
providing feedback from the monitoring of the plurality of flash memory channels by page monitors to a load balancing module;
evaluating, using the load balancing module within the Solid State Device, identified Input/Output requests to determine a load of one or more of the plurality of flash memory channels;
assigning a destination flash memory channel out of the plurality of flash memory channels to the write request to a least loaded logical channel group based on the determined load; and
instructing a multiplexer switch to make a connection between an appropriate queue to logical channels to route a command using one of a round robin and a rotational scheme.
2. The method of claim 1 , wherein the identified Input/Output requests comprise write requests.
3. The method of claim 1 , wherein the identified Input/Output requests comprise read requests.
4. The method of claim 1 , further comprising:
monitoring free pages in the Solid State Device associated with the plurality flash memory channels.
5. The method of claim 1 , wherein the flash memory channels comprise groupings of logical channels and monitoring is organized by groups of logical flash memory channels.
6. The method of claim 1 , wherein the flash memory channels comprise groupings of physical channels and monitoring is organized by groups of physical flash memory channels.
7. The method of claim 1 , wherein monitoring a plurality flash memory channels to identify Input/Output requests comprises counting a number of pages transferred per second for each of the plurality of flash memory channels.
8. The method of claim 1 , wherein monitoring a plurality flash memory channels to identify Input/Output requests comprises counting a number of words transferred per second for each of the plurality of flash memory channels.
9. The method of claim 1 , wherein assigning a destination flash memory channel out of the plurality of flash memory channels to the write request based on the determined load comprises a current load of Input/Output requests.
10. The method of claim 1 , wherein the assigning a destination flash memory channel out of the plurality of flash memory channels to the write request based on the determined load comprises a historical load of Input/Output requests.
11. The method of claim 1 , wherein assignment of the write request is based on a Quality of Service level associated with the write request.
12. The method of claim 1 , wherein in the event a load on each of the plurality of flash memory channels is within a specified range, assignment of the write request to one of the plurality of flash memory channels is performed on a round robin rotation.
13. A system for reducing Solid State Device Input/Output latency, the system comprising:
a storage media device; and
a device controller associated with the storage media device, wherein the device controller is configured to:
receive a write request at a Solid State Device;
monitor a plurality of flash memory physical channels to identify Input/Output requests through page monitors;
provide feedback from the monitoring of the plurality of flash memory physical channels by page monitors to a load balancing module within the Solid State Device;
evaluate, using load balancing circuitry, identified Input/Output requests to determine a load of one or more of the plurality of flash memory channels; and
assign a destination flash memory channel out of the plurality of flash memory channels to the write request to a least loaded logical channel group based on the determined load; and
instructing a multiplexer switch to make a connection between an appropriate queue to logical channels to route a command using one of a round robin and a rotational scheme.
14. The system of claim 13 , wherein the identified Input/Output requests comprise write requests.
15. The system of claim 14 , wherein the identified Input/Output requests comprise read requests.
16. The system of claim 14 , further comprising:
monitoring free pages in the Solid State Device associated with the plurality flash memory channels.
17. The system of claim 14 , wherein the plurality of flash memory channels comprise groupings of logical channels and monitoring is organized by groups of logical flash memory channels.
18. The system of claim 14 , wherein the plurality of flash memory channels comprise groupings of physical channels and monitoring is organized by groups of physical flash memory channels.
19. The system of claim 14 , wherein monitoring a plurality flash memory channels to identify Input/Output requests comprises counting a number of pages transferred per second for each of the plurality of flash memory channels.
20. The system of claim 14 , wherein monitoring a plurality flash memory channels to identify Input/Output requests comprises counting a number of words transferred per second for each of the plurality of flash memory channels.