IP Library Granted Patent US 11,264,562
Granted Patent B1
US 11,264,562 · App. 17/004,690 · Granted Mar 1, 2022

Multiferroic-assisted voltage controlled magnetic anisotropy memory device and methods of manufacturing the same

Inventors: Bhagwati Prasad (San Jose, CA); Alan Kalitsov (San Jose, CA); Neil Smith (San Jose, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
H01L43/02G11C11/161G11C11/1673G11C11/1675H01L27/222H01L43/10
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Quick Facts
Patent No.
US 11,264,562
App. No.
17/004,690
Granted
Mar 1, 2022
Kind
B1
Abstract

A magnetic memory device includes a first electrode, a second electrode, and a layer stack located between the first electrode and the second electrode. The layer stack includes a reference layer, a tunnel barrier layer, a free layer, and a magnetoelectric multiferroic layer including at least one crystalline grain. The magnetization of the magnetoelectric multiferroic layer may be axial, canted, or in-plane. For axial or canted magnetization of the magnetoelectric multiferroic layer, a deterministic switching of the free layer may be achieved through coupling with the axial component of magnetization of the magnetoelectric multiferroic layer. Alternatively, the in-plane magnetization of the magnetoelectric multiferroic layer may be employed to induce precession of the magnetization angle of the free layer.

Claims (26)

1. A magnetic memory device, comprising:

a first electrode;

a second electrode; and

a layer stack located between the first electrode and the second electrode and comprising, from one side to another, a reference layer, a tunnel barrier layer, a free layer, and a voltage controlled magnetic anisotropy (VCMA) assist structure having an in-plane magnetization direction, wherein the VCMA assist structure comprises a magnetoelectric multiferroic layer including at least one crystalline grain having an easy axis of magnetization that is parallel to an interface between the free layer and the tunnel barrier layer, and a net in-plane magnetization of the magnetoelectric multiferroic layer is non-zero.

2. The magnetic memory device of claim 1 , wherein the magnetoelectric multiferroic layer has a net ferroelectric polarization that is parallel to the interface between the free layer and the tunnel barrier layer.

3. The magnetic memory device of claim 1 , wherein the magnetoelectric multiferroic layer is polycrystalline, wherein a predominant subset in volume of crystalline grains within the magnetoelectric multiferroic layer has a respective magnetization direction that is aligned to, or has an angle less than 145 degrees from a direction of the net in-plane magnetization of the magnetoelectric multiferroic layer.

4. The magnetic memory device of claim 3 , wherein the net in-plane magnetization of the magnetoelectric multiferroic layer is parallel to or is antiparallel to the direction of the net in-plane magnetization of the magnetoelectric multiferroic layer.

5. The magnetic memory device of claim 1 , wherein the magnetoelectric multiferroic layer comprises a material selected from BiFeO 3 , h-YMnO 3 , BaNiF 4 , PbVO 3 , BiMnO 3 , LuFe 2 O 4 , HoMn 2 O 5 , h-HoMnO 3 , h-ScMnO 3 , h-ErMnO 3 , h-TmMnO 3 , h-YbMnO 3 , h-LuMnO 3 , K 2 SeO 4 , Cs 2 CdI 4 , TbMnO 3 , Ni 3 V 2 O 8 , MnWO 4 , CuO, ZnCr 2 Se 4 , LiCu 2 O 2 , and Ni 3 B 7 O 13 I.

6. The magnetic memory device of claim 5 , wherein the magnetoelectric multiferroic layer comprises a BiFeO 3 layer having a (111) preferred grain orientation and a thickness of 1 nm or less.

7. The magnetic memory device of claim 1 , wherein the VCMA assist structure comprises a ferromagnetic layer having an in-plane magnetization direction and an electrically conductive nonmagnetic spacer layer located between the free layer and the ferromagnetic layer.

8. The magnetic memory device of claim 1 , wherein the VCMA assist structure comprises a ferrimagnetic layer having an in-plane magnetization direction and an electrically conductive nonmagnetic spacer layer located between the free layer and the ferrimagnetic layer.

9. The magnetic memory device of claim 1 , wherein the layer stack further comprises a nonmagnetic capping layer including a nonmagnetic metal contacting the magnetoelectric multiferroic layer and one of the electrode and the second electrode.

10. The magnetic memory device of claim 1 , wherein the layer stack further comprises a SAF structure contacting the reference layer.

11. The magnetic memory device of claim 1 , wherein the tunnel barrier layer comprises a dielectric layer having a thickness of 1 nm to 2 nm.

12. The magnetic memory device of claim 1 , further comprising a sensing circuit configured to determine tunneling magnetoresistance of the layer stack between the first electrode and the second electrode.

13. The magnetic memory device of claim 12 , further comprising programming circuit connected to the first electrode and the second electrode and configured to non-deterministically program the magnetic memory device using non-deterministic VCMA programming.

14. The magnetic memory device of claim 13 , wherein the programming circuit is configured to:

to determine whether a memory state of the magnetic memory device is in a target state or not by comparing a measured value of the tunneling magnetoresistance of the layer stack to a target value; and

to apply a programming voltage pulse that induces precession of an angle between a magnetization direction of the free layer and an axial direction that is perpendicular to the interface between the free layer and the tunnel barrier layer if the magnetic memory device is not in the target state, and not to apply any programming voltage pulse if the magnetic memory device is in the target state.

15. The magnetic memory device of claim 14 , wherein the in-plane magnetization of the VCMA assist structure induces precession of the angle between the magnetization direction of the free layer and the axial direction between 0 degree and 180 degrees upon application of the programming voltage pulse without applying an external magnetic field.

16. A method of operating the magnetic memory device of claim 1 , comprising determining tunneling magnetoresistance of the layer stack.

17. The method of claim 16 , further comprising non-deterministically programming the magnetic memory device without applying an external magnetic field by applying a VCMA programming voltage pulse between the first electrode and the second electrode.

18. The method of claim 17 , further comprising:

determining whether a memory state of the magnetic memory device is in a target state or not by comparing a measured value of the tunneling magnetoresistance of the layer stack to a target value; and

applying the VCMA programming voltage pulse that induces a precession of an angle between a magnetization direction of the free layer and an axial direction that is perpendicular to the interface between the free layer and the tunnel barrier layer if the magnetic memory device is not in the target state, and not applying any programming voltage pulse if the magnetic memory device is in the target state.

19. The method of claim 18 , wherein a duration of the programming voltage pulse is selected such that the angle between the magnetization direction and the axial direction changes by more than 135 degrees at an end of the programming voltage pulse.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 054475 FRAME 0421 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0358 →
SECURITY INTEREST Recorded Nov 18, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 054475/0421 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2020
From: PRASAD, BHAGWATI; KALITSOV, ALAN; SMITH, NEIL
To: WESTERN DIGITAL TECHNOLOGIES, INC.,
Reel/Frame 053617/0773 →