IP Library Granted Patent US 11,073,570
Granted Patent B1
US 11,073,570 · App. 16/885,655 · Granted Jul 27, 2021

Detecting problematic voltage signals from charge pumps

Inventors: Liang Li (Shanghai, CN); Hui Jia (Shanghai, CN); Qin Zhen (Shanghai, CN)
Assignee: Western Digital Technologies, Inc.
G01R31/40
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Quick Facts
Patent No.
US 11,073,570
App. No.
16/885,655
Granted
Jul 27, 2021
Kind
B1
Abstract

Techniques and apparatuses are provided for testing a charge pump. A test circuit detects voltage drop-offs in a voltage signal provided by a charge pump in a test period. A comparator is used to compare the voltage signal to a divided down, delayed version of the signal. A counting circuit is connected to an output of the comparator to determine a number of the drop-offs in the test period. A control circuit such as an on-chip state machine compares the number of drop-offs to a maximum allowable number of drop-offs to set a pass/fail status of the charge pump. The control circuit can configure various parameters of the test, including a ratio of a voltage divider, and the maximum allowable number of drop-offs based on the charge pump being tested.

Claims (54)

1. An apparatus, comprising:

a comparator comprising a first input path and a second input path, the first input path is connected to a charge pump and the second input path is connected to the first input path;

a first voltage divider and a delay circuit in the second input path;

a counting circuit connected to an output path of the comparator and configured to count a number of transitions in the output path of the comparator during a test period; and

a control circuit connected to the counting circuit and configured to receive the count from the counting circuit and compare the count to a maximum allowable number of transitions.

2. The apparatus of claim 1 , wherein:

a voltage signal in the second input path is a delayed and divided down version of a voltage signal in the first input path.

3. The apparatus of claim 1 , wherein:

the control circuit is configured to provide a request to the charge pump to output a fixed voltage during the test period; and

each transition corresponds to a downward transition in a voltage on the first input path, where the downward transition is more than a guard band voltage set by the first voltage divider.

4. The apparatus of claim 1 , further comprising:

a second voltage divider connected to the charge pump, the first input path is connected to the second voltage divider to receive a divided down version of a voltage signal output by the charge pump.

5. The apparatus of claim 4 , wherein:

the first voltage divider receives the divided down version of the voltage signal output by the charge pump; and

the first voltage divider divides down the divided down version of the voltage signal output by the charge pump to provide a guard band voltage.

6. The apparatus of claim 1 , wherein:

the first voltage divider is in a set of voltage dividers, the set of voltage dividers is configured to divide a voltage according to a plurality of ratios; and

the control circuit is configured to provide a signal to the set of voltage dividers selecting a ratio of the plurality of ratios.

7. The apparatus of claim 1 , wherein:

the control circuit is configured to select the maximum allowable number of transitions from among a plurality of maximum allowable numbers of transitions.

8. The apparatus of claim 1 , wherein:

the control circuit is configured to set a pass/fail status for the charge pump based on a comparison of the number of transitions in the output signal to a maximum allowable number of transitions.

9. The apparatus of claim 1 , wherein:

the control circuit is configured to provide a signal to the delay circuit to select a delay among a plurality of delays.

10. The apparatus of claim 1 , further comprising:

a multiplexer connected to output paths of a plurality of charge pumps, the control circuit is configured to provide a signal to the multiplexer selecting the charge pump from among a plurality of charge pumps.

11. The apparatus of claim 10 , wherein:

the first voltage divider is configured to divide a voltage according to a plurality of ratios; and

the control circuit is configured to provide a signal to the first voltage divider selecting a ratio of the plurality of ratios, the ratio is based on the selected charge pump.

12. The apparatus of claim 10 , wherein:

the control circuit is configured to select the maximum allowable number of transitions from among a plurality of maximum allowable numbers of transitions; and

the selected maximum allowable number of transitions is based on the selected charge pump.

13. A method, comprising:

at a control circuit, comparing a first voltage signal on a first path to a second voltage signal on a second path in a test period, the second voltage signal comprises a delayed and divided down version of the first voltage signal, the first path is connected to a charge pump and the comparing detects a number of drop-offs in a voltage output of the charge pump while the charge pump is requested to output a fixed voltage; and

based on the number of drop-offs, setting a pass/fail status for the charge pump.

14. The method of claim 13 , wherein:

each drop-off comprises a decrease in a voltage of the voltage signal on the first path below a voltage of the voltage signal on the second path.

15. The method of claim 13 , further comprising:

selecting the charge pump from among a plurality of charge pumps; and

determining a maximum allowable number of drop-offs based on the selected charge pump, wherein the pass/fail status is set by comparing a number of the drop-offs to the maximum allowable number of drop-offs.

16. An apparatus, comprising:

a memory die comprising a plurality of non-volatile memory cells;

a plurality of charge pumps on the memory die;

a multiplexer on the memory die, the multiplexer is connected to the plurality of charge pumps;

a comparator on the memory die, the comparator comprising a first input path and a second input path, the first input path is connected to the multiplexer and the second input path is connected to the first input path, the second input path comprising a voltage divider and a delay circuit; and

a control circuit, the control circuit is configured to select a charge pump of the plurality of the charge pumps, and to control the multiplexer to pass a voltage signal from the selected charge pump to the first input path.

17. The apparatus of claim 16 , wherein:

the control circuit is configured to set a ratio of the voltage divider based on the selected charge pump.

18. The apparatus of claim 16 , wherein:

in a test period in which the selected charge pump is requested to provide a voltage signal at a fixed level, the control circuit is configured to determine a number of times a voltage on the first input path falls below a voltage on the second input path and to compare the number to a maximum allowable number.

19. The apparatus of claim 18 , wherein:

the control circuit is configured to select the maximum allowable number based on the selected charge pump.

20. The apparatus of claim 18 , wherein:

the control circuit is configured to set a fail status for the selected charge pump when the number exceeds the maximum allowable number.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2020
From: LI, LIANG; JIA, HUI; ZHEN, QIN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052775/0417 →
Cited By (1)
US 12,348,132