Thread-aware controller
A controller includes one or more hardware components for performing operations, an interconnect, and a plurality of processors connected to the one or more hardware components through the interconnect. Each processor of the plurality of processors is configured to perform multithreading to concurrently handle multiple threads of execution, and assign a different thread identifier or master ID value to each concurrently handled thread of execution. An instruction is generated for a hardware component by executing a thread of the concurrently handled threads of execution. The instruction includes the thread identifier or indicates the master ID value assigned to the thread. The generated instruction is sent to the hardware component through the interconnect.
1. A controller, comprising:
one or more hardware components for performing operations;
an interconnect; and
a plurality of processors connected to the one or more hardware components through the interconnect, wherein each processor of the plurality of processors is configured to:
perform multithreading to concurrently handle multiple threads of execution;
assign a different master ID value to each concurrently handled thread of execution;
generate an instruction for a hardware component of the one or more hardware components by executing a thread of the concurrently handled threads of execution, wherein the instruction indicates the master ID value assigned to the thread; and
send the generated instruction to the hardware component through the interconnect, wherein the hardware component is configured to block access to a resource of the hardware component by the thread based on the master ID value indicated by the instruction.
2. The controller of claim 1 , wherein each processor of the plurality of processors includes a local master ID register for storing the master ID values assigned to the concurrently handled threads of execution.
3. The controller of claim 2 , wherein each processor of the plurality of processors is further configured to indicate in the local master ID register the master ID value assigned to a thread that is currently being executed by the processor.
4. The controller of claim 1 , wherein the plurality of processors includes at least one Reduced Instruction Set Computer (RISC) processor.
5. The controller of claim 1 , wherein the concurrently handled threads of execution are firmware threads for controlling a data storage device.
6. The controller of claim 1 , wherein the hardware component is further configured to determine whether to perform the instruction received from the processor based on the master ID value indicated by the instruction.
7. The controller of claim 1 , wherein the hardware component includes a plurality of registers for storing data, and wherein the hardware component is further configured to:
allocate a first portion of the plurality of registers to a first master ID value indicated by a first instruction received from the processor;
receive a different instruction from a different processor of the plurality of processors while performing the first instruction, the different instruction indicating a different master ID value assigned to a different thread being executed by the different processor; and
allocate a second portion of the plurality of registers to the different master ID value indicated by the different instruction received from the different processor.
8. The controller of claim 1 , wherein the hardware component is further configured to prioritize performance of a first instruction over a different instruction based on the indication of the master ID value for the thread.
9. A data storage device comprising the controller of claim 1 .
10. A method for operating a controller, the method comprising:
using a processor of the controller to perform multithreading to concurrently handle multiple threads of execution;
assigning a different thread identifier to each concurrently handled thread of execution;
generating an instruction for a hardware component of the controller by executing a thread of the concurrently handled threads of execution, wherein the instruction indicates the thread identifier for the thread; and
sending the generated instruction to the hardware component for performing the instruction, wherein the hardware component blocks access by the thread to a resource of the hardware component based on the thread identifier indicated by the instruction.
11. The method of claim 10 , further comprising storing the thread identifiers assigned to the concurrently handled threads of execution in a register of the processor.
12. The method of claim 11 , further comprising indicating in the register the thread identifier assigned to a thread that is currently being executed by the processor.
13. The method of claim 10 , wherein the concurrently handled threads of execution are firmware threads for controlling a data storage device.
14. The method of claim 10 , further comprising determining by the hardware component whether to perform the instruction received from the processor based on the thread identifier included in the instruction.
15. The method of claim 10 , wherein the hardware component includes a plurality of registers for storing data, and wherein the method further comprises:
allocating a first portion of the plurality of registers to a first thread identifier indicated by a first instruction;
receiving a different instruction from a different processor of the controller while performing the first instruction, the different instruction indicating a different thread identifier assigned to a different thread being executed by the different processor; and
allocating a second portion of the plurality of registers to the different thread identifier indicated by the different instruction received from the different processor.
16. The method of claim 10 , further comprising prioritizing performance of a first instruction by the hardware component over a different instruction based on the indication of the thread identifier.
17. A non-transitory computer readable medium storing computer-executable instructions, wherein when the computer-executable instructions are executed by a controller, the computer-executable instructions cause the controller to:
perform multithreading to concurrently handle multiple threads of execution at a processor of the controller;
assign a different master ID value to each concurrently handled thread of execution at the processor;
generate an instruction for a hardware component by executing a thread of the concurrently handled threads of execution, wherein the instruction indicates the master ID value assigned to the thread; and
send the generated instruction to the hardware component, wherein the hardware component blocks access by the thread to a resource of the hardware component based on the master ID value indicated by the instruction.
18. The non-transitory computer readable medium of claim 17 , wherein when the computer-executable instructions are executed by the controller, the computer-executable instructions further cause the hardware component to determine whether to perform the instruction based on the master ID value assigned to the thread.