IP Library Granted Patent US 9,323,663
Granted Patent B2
US 9,323,663 · App. 13/927,740 · Granted Apr 26, 2016

Managing the write performance of an asymmetric memory system

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Quick Facts
Patent No.
US 9,323,663
App. No.
13/927,740
Granted
Apr 26, 2016
Kind
B2
Abstract

Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.

Claims (44)

1. A method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices, the method comprising:

receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem;

categorizing the write requests into subgroups of write requests based on a characteristic of each write request, where write requests within respective subgroups are mutually exclusive;

ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem by determining a queue occupancy ratio of pending write requests as well as an arrival rate of write requests associated with the particular NVRAM device;

subsequently identifying a target location on at least one NVRAM device of the NVRAM-based storage subsystem to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem, the NVRAM-based storage subsystem in communication with an intermediate volatile storage; and

servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.

2. The method of claim 1 , further comprising:

comparing the ascertained load condition to a load threshold; and

based on the comparison yielding that the ascertained load condition is within the load threshold, writing the corresponding units of data as asynchronous writes through an intermediate volatile storage on the NVRAM-based storage subsystem to the identified target location on the at least one NVRAM device, wherein the asynchronous writes are carried out by sending the respective units of data to the intermediate volatile storage and without confirming that the respective units of data of the write requests have been completely written to the target locations on the at least one NVRAM device of the NVRAM-based storage subsystem.

3. The method of claim 1 , further comprising:

comparing the ascertained load condition to a load threshold; and

based on the comparison yielding that the ascertained load condition is above the load threshold, writing the corresponding units of data as synchronous writes through the intermediate volatile storage on the NVRAM-based storage subsystem to the identified target location on the at least one NVRAM device or bypassing the intermediate volatile storage on the NVRAM-based storage subsystem, wherein the synchronous writes are performed by blocking application processes or threads on the host computing device that have issued the write requests until the respective units of data have been completely written to the at least one NVRAM device of the NVRAM-based storage subsystem.

4. The method of claim 1 , wherein ascertaining the load condition of a particular NVRAM device of the NVRAM-based storage subsystem comprises determining a number of pending I/O access requests at the particular NVRAM device.

5. The method of claim 1 , wherein ascertaining the load condition of a particular NVRAM device of the NVRAM-based storage subsystem comprises determining a number of application processes or threads with I/O access backlogs at the particular NVRAM device.

6. The method of claim 1 , wherein ascertaining the load condition of a particular NVRAM device of the NVRAM-based storage subsystem comprises determining an availability of physical cells on the particular NVRAM device.

7. The method of claim 1 , wherein determining the queue occupancy ratio comprises analyzing a queue of pending write requests at a controller on the particular NVRAM device or analyzing a queue of pending write requests at a device driver on a computing device hosting the NVRAM-based storage system.

8. The method of claim 1 , wherein determining the queue occupancy ratio comprises detecting whether a particular queue of write requests has more than a threshold number of entries.

9. The method of claim 1 , wherein ascertaining a load condition of each of several of the NVRAM devices comprises ascertaining load conditions of candidate erase blocks on the corresponding NVRAM device, and

wherein identifying a target location on at least one NVRAM device further comprises choosing, based on the ascertained load conditions of candidate erase blocks on the corresponding NVRAM devices, an active erase block that comprises more than one write page to accommodate a respective unit of data of a particular write request.

10. A system comprising a non-volatile random-access memory (NVRAM) based storage subsystem, the NVRAM-based storage subsystem comprising at least one NVRAM device in communication with a host computing device, the NVRAM-based storage subsystem is configured to perform the operations of:

receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem;

categorizing the write requests into subgroups of write requests based on a characteristic of each write request, where write requests within respective subgroups are mutually exclusive;

ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem by determining a queue occupancy ratio of pending write requests as well as an arrival rate of write requests associated with the particular NVRAM device;

subsequently identifying a target location on at least one NVRAM device of the NVRAM-based storage subsystem to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem, the NVRAM-based storage subsystem in communication with an intermediate volatile storage; and

servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.

11. The system of claim 10 , wherein the operations further comprise:

comparing the ascertained load condition to a load threshold; and

based on the comparison yielding that the ascertained load condition is within the load threshold, writing the corresponding units of data as asynchronous writes through an intermediate volatile storage on the NVRAM-based storage subsystem to the target location on the at least one NVRAM device, wherein the asynchronous writes are carried out by sending the respective units of data to the intermediate volatile storage and without confirming that the respective units of data of the write requests have been completely written to the target locations on the at least one NVRAM device of the NVRAM-based storage subsystem.

12. The system of claim 10 , wherein the operations further comprise:

comparing the ascertained load condition to a load threshold; and

based on the comparison yielding that the ascertained load condition is above the load threshold, writing the corresponding units of data as synchronous writes through the intermediate volatile storage on the NVRAM-based storage subsystem to the target location on the at least one NVRAM device or bypassing the intermediate volatile storage on the NVRAM-based storage subsystem, wherein the synchronous writes are performed by blocking application processes or threads on the host computing device that have issued the write requests until the respective units of data have been completely written to the at least one NVRAM device of the NVRAM-based storage subsystem.

13. The system of claim 10 , wherein ascertaining the load condition of a particular NVRAM device of the NVRAM-based storage subsystem comprises determining a number of pending I/O access requests at the particular NVRAM device.

14. The system of claim 10 , wherein ascertaining the load condition of a particular NVRAM device of the NVRAM-based storage subsystem comprises determining a number of application processes or threads with I/O access backlogs at the particular NVRAM device.

15. The system of claim 10 , wherein ascertaining the load condition of a particular NVRAM device of the NVRAM-based storage subsystem comprises determining an availability of physical cells on the particular NVRAM device.

16. The system of claim 10 , wherein determining the queue occupancy ratio comprises analyzing a queue of pending write requests at a controller on the particular NVRAM device or analyzing a queue of pending write requests at a device driver on a computing device hosting the NVRAM-based storage system.

17. The system of claim 10 , wherein determining the queue occupancy ratio comprises detecting whether a particular queue of write requests has more than a threshold number of entries.

18. The system of claim 10 , wherein ascertaining a load condition of each of several of the NVRAM devices comprises ascertaining load conditions of candidate erase blocks on the corresponding NVRAM device, and

wherein identifying a target location on at least one NVRAM device further comprises choosing, based on the ascertained load conditions of candidate erase blocks on the corresponding NVRAM devices, an active erase block that comprises more than one write page to accommodate a respective unit of data of a particular write request.

19. A non-transitory machine readable medium, comprising software instructions, which software instructions when executed causes a non-volatile random-access memory (NVRAM) based storage subsystem, which NVRAM based storage subsystem comprising at least one NVRAM device in communication with a host computing device, to perform the operations of:

receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem;

categorizing the write requests into subgroups of write requests based on a characteristic of each write request, where write requests within respective subgroups are mutually exclusive;

ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem by determining a queue occupancy ratio of pending write requests as well as an arrival rate of write requests associated with the particular NVRAM device;

subsequently identifying a target location on at least one NVRAM device of the NVRAM-based storage subsystem to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem, the NVRAM-based storage subsystem in communication with an intermediate volatile storage; and

servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.

Assignments (13)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2020
From: VIRIDENT SYSTEMS, LLC
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053180/0472 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SERIAL NUMBER 13/827,871 PREVIOUSLY RECORDED ON REEL 042463 FRAME 0876. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded May 24, 2017
From: VIRIDENT SYSTEMS, INC.
To: VIRIDENT SYSTEMS, LLC
Reel/Frame 042657/0640 →
CHANGE OF NAME Recorded May 15, 2017
From: VIRIDENT SYSTEMS, INC.
To: VIRIDENT SYSTEMS, LLC
Reel/Frame 042463/0876 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2013
From: KARAMCHETI, VIJAY; SINGHAI, ASHISH; MONDAL, SHIBABRATA; KUMAR, AJITH
To: VIRIDENT SYSTEMS INC.
Reel/Frame 031210/0472 →