Video processing in a data storage device
A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.
1. A controller for a data storage device, comprising:
a memory comprising computer-readable instructions; and
a processor configured to execute the computer-readable instructions that will cause the processor to:
store a portion of a first I-frame comprising a first macroblock on a jumbo block spanning multiple NAND dies;
determine a motion vector of the first macroblock; and encode a P-frame based on the first I-frame and the first macroblock;
store a second I-frame comprising a second macroblock;
autocorrelate the first macroblock with the second macroblock;
store the first macroblock and second macroblock on a NAND die;
and either:
reorder the first macroblock and second macroblock to physically locate each on the NAND die; or
duplicate information of the first macroblock and second macroblock and cause the duplicate information to be physically located on the NAND die.
2. The controller of claim 1 , wherein the computer-readable instructions further cause the processor to optimize ECC performance of a tunable ECC based on at least one of the first I-frame, second I-frame, and P-frame.
3. The controller of claim 1 , wherein the computer-readable instructions further cause the processor to optimize ECC performance of a tunable ECC based on a size of the motion vector.
4. The controller of claim 1 , wherein the computer-readable instructions further cause the processor to maintain a count of usage of one of the first I-frame, second I-frame, or P-frame, and optimize ECC performance of a tunable ECC based on the count.