Sub-block mode (SBM) pre-charge operation sequences
Embodiments of the disclosed technology relate to the operation of memory devices, and more particularly to sub-block mode (SBM) pre-charge operation sequences. One example embodiment provides a novel logic design of the control circuitry of a memory device using comments/instructions for the control circuitry. By virtue of the features of the disclosed technology, the control circuitry can effect pre-charging of an inner or middle vertical sub-block of a NAND string in a memory array. In some examples the NAND string has at least three vertical sub-blocks of non-volatile memory cells.
1 . A method for pre-charging an inner vertical sub-block of a NAND string in a memory array, the NAND string having at least three vertical sub-blocks of non-volatile memory cells, each vertical sub-block having a plurality of wordlines, the NAND string having a source side and a drain side, a first dummy wordline (DS) at the source side, a second dummy wordline (DD) at the drain side, a source-side select gate transistor (SGS) at the source side configured to couple the NAND string to a source line, and a drain-side select gate transistor (SGD) at the drain side configured to couple the NAND string to a bit line, the method comprising:
generating a first hole at the source side of the NAND string and a second hole at the drain side of the NAND string by applying negative voltage at the SGS, negative voltage at the SGD, and positive voltage at every wordline of the NAND string including the first and second dummy wordlines;
transferring each hole towards the inner vertical sub-block by applying negative voltage on a respective next wordline adjacent to each respective hole and on a same side as the inner vertical sub-block to move each respective hole to the respective next wordline, while applying positive voltage on every wordline of the NAND string other than the wordlines that the respective holes are at;
repeating the transferring step until the two holes converge at a wordline in the inner vertical sub-block; and
pre-charging the wordline in the inner vertical sub-block that the two holes converged at.
2 . The method of claim 1 , further comprising pre-charging a wordline on each side of the wordline in the inner vertical sub-block.
3 . The method of claim 1 , further comprising biasing the source line and the bit line at a positive voltage greater than an average voltage of every wordline of the NAND string other than the wordlines where the respective holes are.
4 . The method of claim 1 , further comprising repeating the generating and transferring steps with a different negative voltage to achieve a different pre-charge potential.
5 . The method of claim 1 , wherein
the negative voltage at the SGS and at the SGD is negatively biased so as to generate the holes necessary for pre-charge,
an average positive voltage of every wordline of the NAND string, other than the wordlines where the respective holes are, is a maximum voltage of a programmed cell, and
the source line and bit line are each at a positive bias so as to create gate-induced drain lowering (GIDL) and generate the holes.
6 . The method of claim 1 , wherein the inner sub-block is a middle sub-block.
7 . An apparatus, comprising:
a NAND string in a memory array, the NAND string having at least three vertical sub-blocks of non-volatile memory cells, each vertical sub-block having a plurality of wordlines, the NAND string having a source side and a drain side, a first dummy wordline (DS) at the source side, a second dummy wordline (DD) at the drain side, a source-side select gate transistor (SGS) at the source side configured to couple the NAND string to a bit source line, and a drain-side select gate transistor (SGD) at the drain side configured to couple the NAND string to a bit line; and
a control circuit, configured to pre-charge an inner vertical sub-block of the NAND string in a program operation, wherein to pre-charge the inner vertical sub-block, the control circuit is configured to:
generate a first hole at the source side of the NAND string and a second hole at the drain side of the NAND string by applying negative voltage at the SGS, negative voltage at the SGD, and positive voltage at every wordline of the NAND string including the first and second dummy wordlines;
transfer each hole towards the inner vertical sub-block by applying negative voltage on a respective next wordline adjacent to each respective hole and on a same side as the inner vertical sub-block to move each respective hole to the respective next wordline, while applying positive voltage on every wordline of the NAND string other than the wordlines that the respective holes are at;
repeat the transfer operation until the two holes converge at a wordline in the inner vertical sub-block; and
pre-charge the wordline in the inner vertical sub-block that the two holes converged at.
8 . The apparatus of claim 7 , wherein the control circuit is further configured to pre-charge a wordline on each side of the wordline in the inner vertical sub-block.
9 . The apparatus of claim 7 , wherein the control circuit is further configured to bias the source line and the bit line at a positive voltage greater than an average voltage of every wordline of the NAND string other than the wordlines where the respective holes are.
10 . The apparatus of claim 7 , wherein the control circuit is further configured to repeat the generate and transfer operations with a different negative voltage to achieve a different pre-charge potential.
11 . The apparatus of claim 7 , wherein
the negative voltage at the SGS and at the SGD is negatively biased so as to generate the holes necessary for pre-charge,
an average positive voltage of every wordline of the NAND string, other than the wordlines where the respective holes are, is a maximum voltage of a programmed cell, and
the source line and bit line are each at a positive bias so as to create gate-induced drain lowering (GIDL) and holes.
12 . The apparatus of claim 7 , wherein the inner sub-block is a middle sub-block.
13 . A non-transitory computer-readable storage medium comprising instructions executable by a processor, the instructions programming the processor to pre-charge an inner vertical sub-block of a NAND string in a memory array, the NAND string having at least three vertical sub-blocks of non-volatile memory cells, each vertical sub-block having a plurality of wordlines, the NAND string having a source side and a drain side, a first dummy wordline (DS) at the source side, a second dummy wordline (DD) at the drain side, a source-side select gate transistor (SGS) at the source side configured to couple the NAND string to a bit source line, and a drain-side select gate transistor (SGD) at the drain side configured to couple the NAND string to a bit line; wherein to pre-charge the inner vertical sub-block, the instructions programming the processor to:
generate a first hole at the source side of the NAND string and a second hole at drain side of the NAND string by applying negative voltage at the SGS, negative voltage at the SGD, and positive voltage at every wordline of the NAND string including the first and second dummy wordlines;
transfer each hole towards the inner vertical sub-block by applying negative voltage on a respective next wordline adjacent to each respective hole and on a same side as the inner vertical sub-block to move each respective hole to the respective next wordline, while applying positive voltage on every wordline of the NAND string other than the wordlines that the respective holes are at;
repeat the transfer operation until the two holes converge at a wordline in the inner vertical sub-block; and
pre-charge the wordline in the inner vertical sub-block that the two holes converged at.
14 . The non-transitory computer-readable storage medium of claim 13 , wherein the instructions further program the processor to pre-charge a wordline on each side of the wordline in the inner vertical sub-block.
15 . The non-transitory computer-readable storage medium of claim 13 , wherein the instructions further program the processor to bias the source line and the bit line at a positive voltage greater than an average voltage of every wordline of the NAND string other than the wordlines that the respective holes are at.
16 . The non-transitory computer-readable storage medium of claim 13 , wherein the instructions further program the processor to repeat the generate and transfer operations with a different negative voltage to achieve a different pre-charge potential.
17 . The non-transitory computer-readable storage medium of claim 13 , wherein
the negative voltage at the SGS and at the SGD is negatively biased so as to generate the holes necessary for pre-charge,
an average positive voltage of every wordline of the NAND string, other than the wordlines where the respective holes are, is a maximum voltage of a programmed cell, and
the source line and bit line are each at a positive bias so as to create gate-induced drain lowering (GIDL) and holes.
18 . The non-transitory computer-readable storage medium of claim 13 , wherein the inner sub-block is a middle sub-block.
19 . A control circuit configured to implement the method of claim 1 .
20 . A memory device having a storage controller comprising the non-transitory computer-readable storage medium of claim 13 .