Grouping memory cells into sub-blocks for program speed uniformity
A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.
1. A memory device, comprising:
a set of NAND strings which extends through a plurality of word line layers, wherein the plurality of word line layers are vertically spaced apart from one another by dielectric layers in a stack, the set of NAND strings comprises one row of NAND strings at one distance from a first edge of the plurality of word line layers and another row of NAND strings at another distance from the first edge of the plurality of word line layers, greater than the one distance; and
a control circuit configured to program the one row of NAND strings and to separately program the another row of NAND strings, wherein the control circuit is configured to program the one row of NAND strings using incremental step pulse programming with one initial program voltage and to program the another row of NAND strings using incremental step pulse programming with another initial program voltage which is higher than the one initial program voltage.
2. The memory device of claim 1 , wherein:
the control circuit is configured to perform the incremental step pulse programming of the one row of NAND strings and the incremental step pulse programming of the another row of NAND strings use a common program voltage step size.
3. The memory device of claim 1 , wherein:
the control circuit is configured to program the one row of NAND strings using incremental step pulse programming with one step size and to program the another row of NAND strings using incremental step pulse programming with another step size which is different than the one step size.
4. The memory device of claim 1 , further comprising:
a set of bit lines, each bit line in the set of bit lines is connected to a NAND string in the one row of NAND strings and to a NAND string in the another row of NAND strings.
5. The memory device of claim 1 , wherein:
the set of NAND strings comprises an additional row of NAND strings at a distance from the first edge of the plurality of word line layers which is greater than the another distance; and
the control circuit is configured to program the additional row of NAND strings separately from the programming of the one row of NAND strings and the programming of the another row of NAND strings.
6. The memory device of claim 5 , wherein:
the control circuit is configured to program the additional row of NAND strings using incremental step pulse programming with an additional initial program voltage which is higher than the another initial program voltage.
7. The memory device of claim 5 , further comprising:
a set of bit lines, each bit line in the set of bit lines is connected to a NAND string in the one row of NAND strings, to a NAND string in the another row of NAND strings and to a NAND string in the additional row of NAND strings.
8. The memory device of claim 1 , wherein:
the set of NAND strings comprises an additional row of NAND strings at the one distance from a second edge of the plurality of word line layers, opposite the first edge; and
the control circuit is configured to program the additional row of NAND strings concurrently with the programming of the one row of NAND strings.
9. The memory device of claim 8 , wherein:
the control circuit is configured to program the additional row of NAND strings using the incremental step pulse programming with the one initial program voltage.
10. The memory device of claim 8 , wherein:
the one row of NAND strings comprise select gate transistors connected to one another;
the another row of NAND strings comprise select gate transistors connected to one another;
the additional row of NAND strings comprise select gate transistors connected to one another;
the select gate transistors of the one row of NAND strings are connected to the select gate transistors of the additional row of NAND strings; and
the select gate transistors of the one row of NAND strings are not connected to the select gate transistors of the another row of NAND strings.
11. The memory device of claim 1 , further comprising:
an isolation area extending through the stack adjacent to the first edge.
12. The memory device of claim 1 , wherein:
a thickness of a block oxide layer in the NAND strings of the one row of NAND strings is less than a thickness of a block oxide layer in the NAND strings of the another row of NAND strings.
13. A method for programming in a memory device, comprising:
concurrently programming a first edge row of NAND strings and a second edge row of NAND strings in a stacked memory device, the stacked memory device comprising alternating conductive layers and dielectric layers; and
separate from the concurrently programming the first edge row of NAND strings and the second edge row of NAND strings, programming an interior row of NAND strings in the stacked memory device, wherein the interior row of NAND strings is between the first edge row of NAND strings and the second edge row of NAND strings.
14. The method of claim 13 , wherein:
the first edge row of NAND strings and the second edge row of NAND strings are in one sub-block of a block; and
the interior row of NAND strings is in another sub-block of the block.
15. The method of claim 13 , wherein:
the concurrently programming the first edge row of NAND strings and the second edge row of NAND strings uses incremental step pulse programming with a first initial program voltage; and
the programming the interior row of NAND strings uses incremental step pulse programming with a second initial program voltage, higher than the first initial program voltage.
16. The method of claim 15 , wherein:
the incremental step pulse programming of the concurrently programming the first edge row of NAND strings and the second edge row of NAND strings, and the incremental step pulse programming of the programming the interior row of NAND strings, use a common program voltage step size.
17. A memory device, comprising:
a plurality of word line layers which are vertically spaced apart from one another by dielectric layers in a sub-block of a block, the sub-block having opposing first and second edges and an interior region between the first and second edges;
a plurality of NAND strings extending vertically through the sub-block, the plurality of NAND strings comprising edge NAND strings adjacent to the first and second edges and interior NAND strings between the edge NAND strings;
means for concurrently programming the first and second edge NAND strings; and
means for programming the interior NAND strings separately from the programming of the first and second edge NAND strings.
18. The memory device of claim 17 , wherein:
a programming parameter used in the programming of the first and second edge NAND strings is different than a programming parameter used in the programming of the interior NAND strings.
19. The memory device of claim 17 , wherein:
an initial program voltage used in the programming of the first and second edge NAND strings is different than an initial program voltage used in the programming of the interior NAND strings.