Methods of operating memory devices based on sub-block positions and related memory system
A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.
1. A memory device comprising:
a lower chip having a peripheral circuit region;
a first upper chip stacked on the lower chip, bonded to the lower chip and having a first cell region; and
a second upper chip stacked on the first upper chip, bonded to the first upper chip and having a second cell region,
wherein the first cell region comprises:
a first substrate formed adjacent to the second upper chip;
a first common source line formed on a lower surface of the first substrate;
a first metal layer formed adjacent to the lower chip and connected to a first bit line; and
a first sub-block configured to perform a program operation in an alignment order of first selected word lines based on a direction from the first common source line to the first bit line, and
wherein the second cell region comprises:
a second substrate;
a second common source line formed on a lower surface of the second substrate;
a second metal layer formed adjacent to the first upper chip and connected to a second bit line;
a second sub-block formed adjacent to the second metal layer and configured to perform a program operation in an alignment order of second selected word lines based on a direction from the second bit line to the second common source line; and
a third sub-block formed adjacent to the second substrate and configured to perform a program operation in an alignment order of third selected word lines based on a third direction from the second common source line toward the second bit line.
2. The memory device of claim 1 , wherein a number of word lines connected to the first sub-block is different from a number of word lines connected to the second sub-block.
3. The memory device of claim 1 , wherein a number of word lines connected to the second sub-block is different from a number of word lines connected to the third sub-block.
4. The memory device of claim 1 , wherein a number of word lines connected to the second sub-block is the same as a number of word lines connected to the third sub-block.
5. The memory device of claim 1 , wherein a number of data bits that are configured to be stored in memory cells included in the first sub-block is different from a number of data bits that are configured to be stored memory cells included in the second sub-block.
6. The memory device of claim 1 , wherein a number of data bits that are configured to be stored in memory cells included in the second sub-block is different from a number of data bits that are configured to be stored in memory cells included in the third sub-block.
7. The memory device of claim 1 , wherein the first cell region further comprises a fourth sub-block configured to perform a program operation in an alignment order of fourth selected word lines based on a direction from the first bit line toward the first common source line.
8. The memory device of claim 1 , wherein a precharge path of the second sub-block is different from a precharge path of the third sub-block.
9. The memory device of claim 8 , wherein:
the precharge path of the second sub-block is formed through the second bit line, and
the precharge path of the third sub-block is formed through the second common source line.
10. A memory device comprising:
a lower chip having a peripheral circuit region;
a first upper chip stacked on the lower chip, bonded to the lower chip, and having a first cell region; and
a second upper chip stacked on the first upper chip, bonded to the first upper chip, and having a second cell region,
wherein:
the first cell region includes:
a first substrate formed adjacent to the second upper chip;
a first common source line formed on a lower surface of the first substrate; and
a first metal layer formed adjacent to the lower chip and connected to a first bit line, and a first sub-block,
the second cell region includes:
a second substrate;
a second common source line formed on a lower surface of the second substrate; and
a second metal layer formed adjacent to the first upper chip and connected to a second bit line, and a second sub-block, and
a program direction of the first sub-block is different from a program direction of the second sub-block.
11. The memory device of claim 10 , wherein:
the first sub-block is configured to be programmed in an alignment order of first selected word lines based on a direction from the first common source line to the first bit line, and
the second sub-block is configured to be programmed in an alignment order of second selected word lines based on a direction from the second bit line toward the second common source line.
12. The memory device of claim 10 , wherein:
the first sub-block is configured to be programmed in an alignment order of first selected word lines based on a direction from the first bit line to the first common source line, and
the second sub-block is configured to be programmed in an alignment order of second selected word lines based on a direction from the second common source line toward the second bit line.
13. The memory device of claim 10 , wherein:
the first cell region further comprises a third sub-block configured to have a program direction that is different from that of the first sub-block, and
the second cell region further comprises a fourth sub-block configured to have a program direction that is different from that of the second sub-block.
14. The memory device of claim 13 , wherein:
the first sub-block is located closer to the lower chip than the third sub-block,
the second sub-block is located closer to the first upper chip than the fourth sub-block,
the first sub-block is configured to be programmed in an alignment order of first selected word lines based on a direction from the first bit line to the first common source line,
the second sub-block is configured to be programmed in an alignment order of second selected word lines based on a direction from the second bit line to the second common source line,
the third sub-block is configured to be programmed in an alignment order of third selected word lines based on a direction from the first common source line to the first bit line, and
the fourth sub-block is configured to be programmed in an alignment order of fourth selected word lines based on a direction from the second common source line to the second bit line.
15. The memory device of claim 13 , wherein:
the first sub-block is pre-charged through a precharge path that is different from that of the third sub-block, and
the second sub-block is pre-charged through a precharge path that is different from that of the fourth sub-block.
16. The memory device of claim 10 , wherein a number of memory cells included in the first sub-block is different from a number of memory cells included in the second sub-block.
17. The memory device of claim 10 , wherein the first cell region further comprises a third sub-block configured to have the same program direction as the second sub-block.
18. The memory device of claim 10 , wherein the second cell region further comprises a fourth sub-block configured to have the same program direction as the first sub-block.