Methods for early write termination with non-volatile memory
View Patent ↗In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.
1. A method for writing data into non-volatile memory in an expansion memory card with a software driver, the method comprising:
issuing a write operation from operating system software or application software to software driver;
transferring write data associated with the write operation to a volatile memory buffer within a memory controller controlling access to one or more non-volatile memory devices (NVMDs) organized in one or more memory channels;
initiating a write operation to one of one or more channel controllers in the memory controller, wherein each of the one or more channel controllers to control one or more NVMDs organized on the same memory channel;
before completion of the write operation in an NVMD, notifying the operating system software or the application software that the write operation is guaranteed to be completed with a probability such that further backup write operations are not needed, even if a power failure and a switching to a backup power source occur thereafter.
2. The method of claim 1 , wherein
the probability that the write operation is guaranteed to be completed with a probability of greater than ninety five percent.
3. The method of claim 1 , wherein
the notifying of the guaranteed completion occurs after the initiating of the write operation and well before the write operation to the NVMD is completed.
4. The method of claim 3 , wherein
the notifying of the guaranteed completion occurs in a time interval less than fifty percent of the write latency of the NVMD.
5. The method of claim 3 , wherein
the notifying of the guaranteed completion occurs in a time interval less than twenty percent of the write latency of the NVMD.
6. The method of claim 3 , wherein
the NVMD is a NAND flash memory; and
the notifying of the guaranteed completion occurs within fifty microseconds of the initiating of the write operation.
7. The method of claim 1 , wherein
the write operation is guaranteed to be completed by
if a power failure occurs,
switching to a card level power source on the expansion card, and
completing any current write operations of write data from the volatile memory buffer to NVMDs.
8. The method of claim 7 , wherein
the write operation is further guaranteed to be completed by
if a power failure occurs,
waiting for completion of a first write operation to write a first write data from the shared buffer to a first NVM location at a first NVMD address in a first memory controller channel;
examining results of the first write operation;
if the first write operation was unsuccessful, then attempting to rewrite the first write data from the shared buffer into a second NVM location at a first NVMD backup address provided by a first backup register in the first memory channel controller.
9. The method of claim 8 , wherein
examining results of the rewrite operation;
if the first rewrite operation was unsuccessful, then attempting to rewrite the first write data from the shared buffer into a third NVM location at a second NVMD backup address provided by a second backup register in the first memory channel controller.
10. The method of claim 9 , wherein
examining results of the rewrite operation;
if the second rewrite operation was unsuccessful, then attempting to rewrite the first write data from the shared buffer into a fourth NVM location at a third NVMD backup address provided by a third backup register in the first memory channel controller.