IP Library Granted Patent US 11,132,255
Granted Patent B2
US 11,132,255 · App. 16/818,949 · Granted Sep 28, 2021

Methods and systems for implementing redundancy in memory controllers

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Quick Facts
Patent No.
US 11,132,255
App. No.
16/818,949
Filed
Mar 13, 2020
Granted
Sep 28, 2021
Kind
B2
Art Unit
2111
USPC
714/766
Abstract

The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.

Claims (65)

1. A storage system, comprising:

data memory elements, comprising a first data memory element, a second data memory element, and a parity data memory element; and

a controller configured to cause:

initializing or resetting the data memory elements to a zero value;

after receiving a first data:

performing a logical operation between the first data and data in the first data memory element, to produce a first output;

storing the first output into the first data memory element;

performing a logical operation between the first data and data in the parity data memory element to produce a first parity output; and

storing the first parity output into the parity data memory element; and

after receiving a second data:

performing a logical operation between the second data and data in the parity data memory element to produce a second parity output; and

storing the second parity output into the parity data memory element.

2. The storage system of claim 1 , wherein after receiving the second data, the controller is configured to cause:

performing a logical operation between the second data and data in the second data memory element, to produce a second output; and

storing the second output into the second data memory element.

3. The storage system of claim 2 , wherein the controller is configured to cause:

transferring the stored first output from the first data memory element to a corresponding first storage element;

transferring the stored second output from the second data memory element to a corresponding second storage element; and

after transferring the stored first output and the stored second output, re-setting the data memory elements to the zero value.

4. The storage system of claim 3 , wherein each of the corresponding first and second storage elements is a non-volatile memory located in an independent media unit.

5. The storage system of claim 1 , wherein data of the first data memory element is restorable from one or more data of the data memory elements in a valid state and data stored in the parity data memory element.

6. The storage system of claim 1 , wherein the logical operation to produce the first output, the logical operation to produce the first parity output, and the logical operation to produce the second parity output are exclusive OR logical operations.

7. The storage system of claim 1 , wherein the controller is configured to cause incrementally storing data into the parity data memory element.

8. A method, comprising:

initializing or resetting data memory elements to a zero value, wherein the data memory elements comprise a first data memory element, a second data memory element, and a parity data memory element;

after receiving a first data:

performing a logical operation between the first data and data in the first data memory element, to produce a first output;

storing the first output into the first data memory element;

performing a logical operation between the first data and data in the parity data memory element to produce a first parity output; and

storing the first parity output into the parity data memory element; and

after receiving a second data:

performing a logical operation between the second data and data in the parity data memory element to produce a second parity output; and

storing the second parity output into the parity data memory element.

9. The method of claim 8 , comprising:

after receiving the second data:

performing a logical operation between the second data and data in the second data memory element, to produce a second output; and

storing the second output into the second data memory element.

10. The method of claim 9 , comprising:

transferring the stored first output from the first data memory element to a corresponding first storage element;

transferring the stored second output from the second data memory element to a corresponding second storage element; and

after transferring the stored first output and the stored second output, re-setting the data memory elements to the zero value.

11. The method of claim 10 , wherein each of the corresponding first and second storage elements is a non-volatile memory located in an independent media unit.

12. The method of claim 8 , wherein data of the first data memory element is restorable from one or more data of the data memory elements in a valid state and data stored in the parity data memory element.

13. The method of claim 8 , wherein the logical operation to produce the first output, the logical operation to produce the first parity output, and the logical operation to produce the second parity output are exclusive OR logical operations.

14. The method of claim 8 , wherein data is stored into the parity data memory element incrementally.

15. An apparatus, comprising:

means for initializing or resetting data memory elements to a zero value, wherein the data memory elements comprise a first data memory element, a second data memory element, and a parity data memory element;

means for receiving a first data;

means for performing a logical operation between the first data and data in the first data memory element, to produce a first output;

means for storing the first output into the first data memory element;

means for performing a logical operation between the first data and data in the parity data memory element to produce a first parity output;

means for storing the first parity output into the parity data memory element;

means for receiving a second data;

means for performing a logical operation between the second data and data in the parity data memory element to produce a second parity output; and

means for storing the second parity output into the parity data memory element.

16. The apparatus of claim 15 , comprising:

means for performing a logical operation between the second data and data in the second data memory element, to produce a second output; and

means for storing the second output into the second data memory element.

17. The apparatus of claim 16 , comprising:

means for transferring the stored first output from the first data memory element to a corresponding first storage element;

means for transferring the stored second output from the second data memory element to a corresponding second storage element; and

after transferring the stored first output and the stored second output, means for re-setting the data memory elements to the zero value.

18. The apparatus of claim 17 , wherein each of the corresponding first and second storage elements is a non-volatile memory located in an independent media unit.

19. The apparatus of claim 15 , wherein data of the first data memory element is restorable from one or more data of the data memory elements in a valid state and data stored in the parity data memory element.

20. The apparatus of claim 15 , wherein the logical operation to produce the first output, the logical operation to produce the first parity output, and the logical operation to produce the second parity output are exclusive OR logical operations.

Assignments (11)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053482 FRAME 0453 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0279 →
SECURITY INTEREST Recorded May 14, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053482/0453 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2020
From: SINGHAI, ASHISH; NARASIMHA, ASHWIN; OKIN, KENNETH ALAN
To: HGST NETHERLANDS B.V.
Reel/Frame 052337/0011 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2020
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052338/0363 →