IP Library Granted Patent US 10,901,632
Granted Patent B2
US 10,901,632 · App. 16/523,956 · Granted Jan 26, 2021

Managing data for a data storage system

Inventors: Kai-Lung Cheng (Irvine, CA); Yun-Tzuo Lai (Irvine, CA); Eugene Lisitsyn (Anaheim, CA); Jerry Lo (Hacienda Heights, CA); Subhash Balakrishna Pillai (Irvine, CA)
Assignee: WESTERN DITIGAL TECHNOLOGIES, INC.
G06F3/0619G06F3/064G06F3/065G06F3/0679G06F12/0246G06F12/0253G06F2212/7201G06F2212/7205G06F2212/7211
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Quick Facts
Patent No.
US 10,901,632
App. No.
16/523,956
Granted
Jan 26, 2021
Kind
B2
Abstract

The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.

Claims (54)

1. A data storage system, comprising:

a non-volatile memory; and

a controller configured to cause:

processing a request to write data, associated with a logical address, to the non-volatile memory;

detecting whether a first physical address, of a first set of physical addresses, in the non-volatile memory is indicated as bad, wherein the first set of physical addresses is associated with a first indicator, and wherein the first physical address is associated with the logical address;

when the first physical address is indicated as bad, maintaining the first indicator associated with the first set of physical addresses and not updating the first indicator, wherein the first physical address indicated as bad is indicative of a failed operation involving the first physical address; and

when the first physical address is not indicated as bad, updating the first indicator associated with the first set of physical addresses and marking the first physical address as invalid.

2. The data storage system according to claim 1 , wherein the controller is configured to cause:

executing a write operation to write data associated with the logical address to a second physical address in the non-volatile memory, wherein the write operation writes metadata comprising the logical address to the second physical address with the data associated with the logical address; and

facilitating mapping of an address mapping table to map the logical address to the second physical address.

3. The data storage system according to claim 1 , wherein the controller is configured to cause:

verifying a bit corresponding to the first physical address in a bit mask, wherein the first physical address is indicated as bad when the bit is set.

4. The data storage system according to claim 3 , wherein the controller is configured to cause:

setting the bit in the bit mask in response to an error occurring during a read operation to read data written to the first physical address.

5. The data storage system according to claim 1 , wherein the non-volatile memory comprises a plurality of non-volatile memory devices, and wherein the first set of physical addresses comprises a respective physical address in each of the plurality of non-volatile memory devices.

6. The data storage system according to claim 1 , wherein the controller is configured to cause:

determining the first indicator associated with the first set of physical addresses is zero; and

designating the first set of physical addresses for erase operations.

7. The data storage system according to claim 1 , wherein the controller is configured to cause:

removing a mapping between the logical address and the first physical address from an address mapping table, in response to determining that the first physical address is indicated as bad.

8. A data storage system, comprising:

means for processing a request to write data, associated with a logical address, to a non-volatile memory;

means for detecting whether a first physical address, of a first set of physical addresses, in the non-volatile memory is indicated as bad, wherein the first set of physical addresses is associated with a first indicator, and wherein the first physical address is associated with the logical address;

when the first physical address is indicated as bad, means for maintaining the first indicator associated with the first set of physical addresses and not updating the first indicator, wherein the first physical address indicated as bad is indicative of a failed operation involving the first physical address; and

when the first physical address is not indicated as bad, means for updating the first indicator associated with the first set of physical addresses and marking the first physical address as invalid.

9. The data storage system according to claim 8 , comprising:

means for initiating a write operation to write the data associated with the logical address to a second physical address in the non-volatile memory, wherein the write operation writes metadata comprising the logical address to the second physical address with the data associated with the logical address; and

means for updating an address mapping table to map the logical address to the second physical address.

10. The data storage system according to claim 8 , comprising:

means for checking a bit corresponding to the first physical address in a bit mask, wherein the first physical address is indicated as bad if the bit is set.

11. The data storage system according to claim 10 , comprising:

means for setting the bit in the bit mask in response to an error occurring during a read operation to read data written to the first physical address.

12. The data storage system according to claim 8 , wherein the non-volatile memory comprises a plurality of non-volatile memory devices, and wherein the first set of physical addresses comprises a respective physical address in each of the plurality of non-volatile memory devices.

13. The data storage system according to claim 8 , further comprising:

means for determining the first indicator associated with the first set of physical addresses is zero; and

means for designating the first set of physical addresses for erase operations.

14. A machine-implemented method, comprising:

processing a request to write data associated with a logical address, to a non-volatile memory;

detecting whether a first physical address, of a first set of physical addresses, in the non-volatile memory is indicated as bad, wherein the first set of physical addresses is associated with a first indicator, and wherein the first physical address is associated with the logical address;

when the first physical address is indicated as bad, maintaining the first indicator associated with the first set of physical addresses and not updating the first indicator, wherein the first physical address indicated as bad is indicative of a failed operation involving the first physical address; and

when the first physical address is not indicated as bad, updating the first indicator associated with the first set of physical addresses and marking the first physical address as invalid.

15. The machine-implemented method of claim 14 , comprising:

initiating a write operation to write the data associated with the logical address to a second physical address in the non-volatile memory, wherein the write operation writes metadata comprising the logical address to the second physical address with the data associated with the logical address; and

updating an address mapping table to map the logical address to the second physical address.

16. The machine-implemented method of claim 14 , comprising:

checking a bit corresponding to the first physical address in a bit mask, wherein the first physical address is indicated as bad when the bit is set.

17. The machine-implemented method of claim 16 , comprising:

setting the bit in the bit mask in response to an error occurring during a read operation to read data written to the first physical address.

18. The machine-implemented method of claim 14 , wherein the non-volatile memory comprises a plurality of non-volatile memory devices, and wherein the first set of physical addresses comprises a respective physical address in each of the plurality of non-volatile memory devices.

19. The machine-implemented method of claim 14 , comprising:

determining the first indicator associated with the first set of physical addresses is zero;

and designating the first set of physical addresses for erase operations.

20. The machine-implemented method of claim 14 , wherein an address mapping table includes a mapping between the logical address and the first physical address, and

wherein the machine-implemented method comprises removing the mapping between the logical address and the first physical address from the address mapping table, in response to determining that the first physical address is indicated as bad.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2019
From: CHENG, KAI-LUNG; LAI, YUN-TZUO; LISITSYN, EUGENE; LO, JERRY; PILLAI, SUBHASH BALAKRISHNA
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 049964/0964 →
Continuity (3)
Continuation 15664667 · Jul 31, 2017
Provisional Application 62525128 · Jun 26, 2017
Related Publication 20190347018A1 · Nov 14, 2019