Non-volatile memory with dynamic wear leveling group configuration
A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to group physical addresses of the set of non-volatile memory cells into groups of configurable sizes and to individually apply wear leveling schemes to non-volatile memory cells of a group.
1. A non-volatile storage apparatus, comprising:
one or more control circuits configured for communication with a set of non-volatile memory cells, the one or more control circuits are configured to group physical addresses of the set of non-volatile memory cells into two or more wear leveling groups including at least a first wear leveling group and a second wear leveling group, apply a first wear leveling scheme to only the first wear leveling group to level wear only between physical addresses of the first wear leveling group, the first wear leveling scheme configured to change logical-to-physical mapping of the first wear leveling group, apply a second wear leveling scheme that is independent of the first wear leveling scheme to only the second wear leveling group to level wear only between physical addresses of the second wear leveling group, the second wear leveling scheme configured to change logical-to-physical mapping of the second wear leveling group, in response to detecting a high level of wear of the first wear leveling group, merge at least the first wear leveling group and the second wear leveling group to form a merged wear leveling group, the second wear leveling group selected based on a low level of wear of the second wear leveling group, and apply a third wear leveling scheme to the merged wear leveling group.
2. The non-volatile storage apparatus of claim 1 wherein the first and second wear leveling groups have N physical units each and the third wear leveling group has 2N physical units.
3. The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are further configured to subsequently split the merged wear leveling group.
4. The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are configured to record the merge in a table.
5. The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are further configured to record one or more media properties including wear of the set of non-volatile memory cells and merge groups of physical addresses according to recorded wear.
6. The non-volatile storage apparatus of claim 4 wherein the one or more control circuits include a Content Addressable Memory (CAM) configured to store the table.
7. The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are further configured to apply at least one of a start gap wear leveling scheme and an Exclusive OR (XOR) wear leveling scheme.
8. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells comprise Phase Change Memory (PCM) cells, Resistive Random Access Memory (ReRAM) cells, or Magnetoresistive Random Access Memory (MRAM cells).
9. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells is formed in a plurality of memory levels disposed above a substrate in a monolithic three-dimensional memory structure.
10. A method, comprising:
performing wear leveling operations on a first wear leveling group according to a first wear leveling scheme over a period of operation including performing an XOR operation on a logical address and a first bit string to obtain a physical address and changing the first bit string to swap logical addresses between pairs of physical addresses of the first wear leveling group;
performing wear leveling operations on a second wear leveling group according to a second wear leveling scheme over the period of operation including performing an XOR operation on a logical address and a second bit string to obtain a physical address and changing the second bit string to swap logical addresses between pairs of physical addresses of the second wear leveling group;
detecting a high level of wear of the first wear leveling group;
in response to detecting the high level of wear of the first wear leveling group, merging at least the first wear leveling group and the second wear leveling group to form a merged wear leveling group, the second wear leveling group selected for the merging based on a low level of wear of the second wear leveling group; and
performing wear leveling operations on the merged wear leveling group according to a third wear leveling scheme over a subsequent period of operation including performing an XOR operation on a logical address and a third bit string to obtain a physical address and changing the third bit string to swap logical addresses between pairs of physical addresses of the merged wear leveling group.
11. The method of claim 10 wherein the first and second wear leveling groups are of equal size.
12. The method of claim 10 wherein performing wear leveling operations according to the third wear leveling scheme includes performing an Exclusive OR (XOR) operation on an n-bit logical address to obtain an n-bit physical address, performing wear leveling operations according to the first wear leveling scheme includes performing an Exclusive OR (XOR) operation on an (n−1)-bit logical address and a first (n−1)-bit string to obtain an (n−1)-bit physical address, and performing wear leveling operations according to the second wear leveling scheme includes performing an Exclusive OR (XOR) operation on an (n−1)-bit logical address and a second (n−1)-bit string to obtain an (n−1)-bit physical address.
13. The method of claim 10 further comprising:
subsequently dividing the merged wear leveling group into two or more subgroups and applying different wear leveling schemes to each of the two or more subgroups.
14. The method of claim 10 further comprising maintaining a table that includes an indicator to indicate that the first and second wear leveling groups were merged and to record the third bit string.
15. The method of claim 10 further comprising maintaining a record of access to a set of non-volatile memory cells of the merged wear leveling group and searching the record of access for one or more patterns of access to the set of non-volatile memory cells, the one or more patterns of access triggering at least one of: dividing the set of non-volatile memory cells and merging the set of non-volatile memory cells with another set of non-volatile memory cells.
16. The method of claim 10 further comprising:
receiving a command that includes a logical address;
determining that the logical address corresponds to the first wear leveling group from a first portion of the logical address;
looking up a table entry for the first wear leveling group;
determining from the table entry that the first wear leveling group was merged into the merged wear leveling group; and
obtaining the third bit string from the table.
17. The method of claim 10 further comprising prior to merging the first and second wear leveling groups to form the merged wear leveling group, changing at least one of the first or second bit strings such that the first and second bit strings are the same.
18. The method of claim 14 further comprising:
storing the table in a Content Addressable Memory (CAM).
19. A system comprising:
means for detecting a pattern of access to a plurality of physical units in a set of non-volatile memory cells in a first period of operation, each physical unit having a physical address, the plurality of physical units forming a first wear leveling group for application of a first wear leveling scheme and a second wear leveling group for application of a second wear leveling scheme, the first and second wear leveling schemes configured to change logical to physical translation a plurality of times in the first period of operation, the first wear leveling scheme applying an XOR operation on a logical address and a first bit string to obtain a physical address, the second wear leveling scheme applying an XOR operation on a logical address and a second bit string to obtain a physical address, the first and second wear leveling groups each containing a first number of physical units;
means for dynamically selecting physical units of the plurality of physical units to form one or more merged wear leveling groups in a second period of operation based on the detected pattern of access to the plurality of physical units in the first period of operation, including selecting a second number of physical units to form a merged wear leveling group that includes all physical units of the first and second wear leveling groups in response to detecting a high level of wear of the first wear leveling group, the second wear leveling group selected based on a low level of wear of the second wear leveling group; and
means for applying a third wear leveling scheme to only the merged wear leveling group including applying an XOR operation on a logical address and a third bit string to obtain a physical address and changing the third bit string to swap logical addresses between pairs of physical addresses of the merged wear leveling group.
20. The system of claim 19 wherein the set of non-volatile memory cells are Phase Change Memory (PCM) cells, Resistive Random Access Memory (ReRAM) cells, or Magnetoresistive Random Access Memory (MRAM cells).