IP Library Granted Patent US 9,323,637
Granted Patent B2
US 9,323,637 · App. 14/135,371 · Granted Apr 26, 2016

Power sequencing and data hardening architecture

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Quick Facts
Patent No.
US 9,323,637
App. No.
14/135,371
Granted
Apr 26, 2016
Kind
B2
Abstract

The various implementations described herein include systems, methods and/or devices used to enable power sequencing and a data hardening module in a storage device. In one aspect, the method includes determining whether a power supply voltage provided to the storage device is lower than an under-voltage threshold. The method further includes, in accordance with a determination that the power supply voltage is lower than the under-voltage threshold, performing a power fail operation, the power fail operation including: (1) signaling a power fail condition to a plurality of controllers on the storage device, (2) transferring data held in volatile memory to non-volatile memory, and (3) removing power from the plurality of controllers on the storage device.

Claims (59)

1. A method of protecting data in a storage device, the method comprising:

determining whether a power supply voltage provided to the storage device is lower than an under-voltage threshold; and

in accordance with a determination that the power supply voltage is lower than the under-voltage threshold, performing a power fail operation, the power fail operation including:

signaling a power fail condition to a plurality of controllers on the storage device, the plurality of controllers including a memory controller and one or more flash controllers;

transferring data held in volatile memory to non-volatile memory, including:

transferring data, including metadata stored in volatile memory of the memory controller, from the memory controller to the one or more flash controllers; and

transferring data, including the metadata, from the one or more flash controllers to the non-volatile memory; and

removing power from the plurality of controllers on the storage device.

2. The method of claim 1 , wherein the one or more flash controllers are coupled by the memory controller to a host interface of the storage device.

3. The method of claim 1 , wherein removing power from the plurality of controllers on the storage device includes:

resetting the memory controller subsequent to transferring data from the memory controller to the one or more flash controllers; and

removing power from the memory controller subsequent to resetting the memory controller.

4. The method of claim 1 , wherein the one or more flash controllers include a first flash controller and a second flash controller, and wherein removing power from the plurality of controllers on the storage device includes:

resetting the first flash controller subsequent to transferring data from the first flash controller to the non-volatile memory;

resetting the second flash controller subsequent to transferring data from the second flash controller to the non-volatile memory; and

removing power from the first and the second flash controllers subsequent to resetting the first and second flash controllers.

5. The method of claim 4 , wherein removing power from the first and the second flash controllers is subsequent to removing power from the memory controller.

6. The method of claim 1 , wherein the power fail operation is performed to completion regardless of whether the power supply voltage returns to a voltage greater than or equal to the under-voltage threshold.

7. The method of claim 1 , wherein the power supply voltage is a voltage supplied by a host system.

8. The method of claim 1 , wherein the power supply voltage is a voltage supplied for serial presence detect (SPD) functionality.

9. The method of claim 1 , wherein the power supply voltage includes a first voltage and a second voltage, and wherein performing the power fail operation includes:

performing the power fail operation in accordance with a determination that the first voltage is lower than a first under-voltage threshold; and

performing the power fail operation in accordance with a determination that the second voltage is lower than a second under-voltage threshold.

10. The method of claim 1 , wherein the power fail operation is performed using power from a reserve energy storage device.

11. The method of claim 1 , wherein the power fail operation is performed using power from an energy storage device on the storage device.

12. The method of claim 11 , wherein the energy storage device includes one or more capacitors.

13. The method of claim 11 , further comprising:

monitoring the energy storage device to ensure capacitors in the energy storage device are charged to at least a first charge level; and

selectively testing one or more capacitors from the energy storage device during operation of the storage device.

14. The method of claim 11 , further comprising:

prior to determining whether the power supply voltage provided to the storage device is lower than the under-voltage threshold:

charging the energy storage device using a higher voltage than the power supply voltage provided to the storage device;

determining whether the energy storage device meets a minimum charge level threshold within a predefined charge time; and

in accordance with a determination that the energy storage device does not meet the minimum charge level threshold in the predefined charge time, preventing operation of the storage device.

15. The method of claim 14 , wherein preventing operation of the storage device includes communicating a failure message to a host system.

16. The method of claim 11 , further comprising discharging the energy storage device subsequent to removing power from the plurality of controllers on the storage device.

17. The method of claim 1 , wherein the non-volatile memory comprises one or more flash memory devices.

18. The method of claim 1 , wherein the storage device includes a dual in-line memory module (DIMM) device.

19. The method of claim 1 , wherein the plurality of controllers on the storage device include at least one non-volatile memory controller and at least one other memory controller other than the at least one non-volatile memory controller.

20. The method of claim 1 , wherein one of the plurality of controllers on the storage device maps double data rate (DDR) interface commands to serial advance technology attachment (SATA) interface commands.

21. A storage device, comprising:

an interface for coupling the storage device to a host system;

a plurality of controllers including a memory controller and one or more flash controllers, each of the plurality of controllers configured to transfer data held in volatile memory to non-volatile memory; and

a data hardening module including one or more processors and an energy storage device, the data hardening module configured to:

determine whether a power supply voltage provided to the storage device is lower than an under-voltage threshold; and

in accordance with a determination that the power supply voltage is lower than the under-voltage threshold, perform a power fail operation, the power fail operation including:

signaling a power fail condition to the plurality of controllers, causing the plurality of controllers to transfer data held in volatile memory to non-volatile memory, the transfer including:

transferring data, including metadata stored in volatile memory of the memory controller, from the memory controller to the one or more flash controllers; and

transferring data, including the metadata, from the one or more flash controllers to the non-volatile memory; and

removing power from the plurality of controllers on the storage device.

22. The storage device of claim 21 , wherein the one or more flash controllers are coupled by the memory controller to a host interface of the storage device.

23. A non-transitory computer readable storage medium, storing one or more programs for execution by one or more processors of a storage device having a plurality of controllers including a memory controller and one or more flash controllers and a data hardening module, the one or more programs including instructions that when executed by the one or more processors of the storage device cause the data hardening module to:

determine whether a power supply voltage provided to the storage device is lower than an under-voltage threshold; and

in accordance with a determination that the power supply voltage is lower than the under-voltage threshold, perform a power fail operation, the power fail operation including:

signaling a power fail condition to the plurality of controllers, causing the plurality of controllers to transfer data held in volatile memory to non-volatile memory, the transfer including:

transferring data, including metadata stored in volatile memory of the memory controller, from the memory controller to the one or more flash controllers; and

transferring data, including the metadata, from the one or more flash controllers to the non-volatile memory; and

removing power from the plurality of controllers on the storage device.

24. The non-transitory computer readable storage medium of claim 23 , wherein the non-transitory computer readable storage medium includes a non-transitory computer readable storage medium associated with each of the plurality of controllers on the storage device and a non-transitory computer readable storage medium associated with the data hardening module.

Assignments (11)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT (AR) Recorded Feb 22, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 066648/0284 →
PATENT COLLATERAL AGREEMENT (DDTL) Recorded Feb 22, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 066648/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2024
From: SANDISK TECHNOLOGIES LLC
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 066114/0298 →
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038807/0948 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2016
From: SANDISK ENTERPRISE IP LLC
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038295/0225 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2014
From: LUCAS, GREGG S.; DELPAPA, KENNETH B.; HERMAN, LACE J.; ELLIS, ROBERT W.
To: SANDISK ENTERPRISE IP LLC
Reel/Frame 032040/0005 →