Apparatus and methods for writing random access memories
An apparatus is provided that includes a memory device including a plurality of sub-arrays, and a memory controller. The memory controller is configured to determine a value of a parameter of a corresponding write pulse for each bit of a word based on a relative importance of each bit, and write each bit of the word to a corresponding one of the plurality of sub-arrays using the corresponding write pulses.
1. An apparatus comprising:
a memory device comprising a plurality of sub-arrays; and
a memory controller configured to:
determine a value of a parameter of a corresponding write pulse for each bit of a word based on a relative importance of each bit; and
simultaneously write each bit of the word to a corresponding one of the plurality of sub-arrays using the corresponding write pulses.
2. The apparatus of claim 1 , wherein the memory controller is configured to determine the value of the parameter of the corresponding write pulse by minimizing a fidelity metric while satisfying a resource metric.
3. The apparatus of claim 2 , wherein the fidelity metric comprises at least one of a mean square error and a peak signal-to-noise ratio, and wherein the resource metric comprises a write energy.
4. The apparatus of claim 1 , wherein the parameter of the corresponding write pulse comprises at least one of a write current, a pulse width, or a write voltage.
5. The apparatus of claim 1 , wherein a most significant bit of the word has a higher relative importance than a least significant bit of the word.
6. The apparatus of claim 1 , wherein the value of the parameter of the corresponding write pulse of a most significant bit of the word is greater than the value of the parameter of the corresponding write pulse of a least significant bit of the word.
7. The apparatus of claim 1 , wherein the parameter of the corresponding write pulse comprises a write current, and wherein a bit position that is of greater relative importance is assigned a greater write current than a bit position that is of lesser relative importance.
8. The apparatus of claim 1 , wherein the parameter of the corresponding write pulse comprises a pulse width, and wherein a bit position that is of greater relative importance is assigned a greater pulse width than a bit position that is of lesser relative importance.
9. The apparatus of claim 1 , memory controller is further configured to determine the value of the parameter of the corresponding write pulse to satisfy a granularity.
10. A method comprising:
determining by a memory controller a value of a parameter of a corresponding write pulse for each bit of a word based on bit position within the word; and
simultaneously writing by the memory controller each bit of the word to a memory device using the corresponding write pulse for each bit,
wherein determining comprises determining the value of the parameter of the corresponding write pulse based on a relative importance of a bit position of each bit of the word.
11. The method of claim 10 , wherein determining the value of the parameter of the corresponding write pulse comprises minimizing a fidelity metric while satisfying a resource metric.
12. The method of claim 11 , wherein the fidelity metric comprises at least one of a mean square error and a peak signal-to-noise ratio, and wherein the resource metric comprises a write energy.
13. The method of claim 10 , wherein the parameter of the corresponding write pulse comprises at least one of a write current, a pulse width, or a write voltage.
14. The method of claim 10 , further comprising determining by the memory controller the value of the parameter of the corresponding write pulse to satisfy a granularity.
15. The method of claim 10 , wherein the word the parameter of the corresponding write pulse comprises a pulse width, and wherein a bit position that is of greater relative importance is assigned a greater pulse width than a bit position that is of lesser relative importance.
16. The method of claim 10 , wherein a most significant bit of the word has a higher relative importance than a least significant bit of the word.
17. The method of claim 10 , wherein the value of the parameter of the corresponding write pulse of a most significant bit of the word is greater than the value of the parameter of the corresponding write pulse of a least significant bit of the word.
18. The method of claim 10 , wherein the parameter of the corresponding write pulse comprises a write current, and wherein a bit position that is of greater relative importance is assigned a greater write current than a bit position that is of lesser relative importance.
19. An apparatus comprising:
a memory device comprising a first sub-array and a second sub-array; and
a memory controller configured to:
simultaneously write a first bit of a first word to the first sub-array using a first write pulse comprising a first write energy and write a second bit of the first word to the second sub-array using a second write pulse comprising a second write energy lower than the first write energy; and
simultaneously write a first bit of a second word to the second sub-array using a third write pulse that comprises a third write energy higher than the second write energy and write a second bit of the second word to the first sub-array using a fourth write pulse that comprises a fourth write energy lower than the first write energy.
20. The apparatus of claim 19 , wherein the first bit of the first word has a higher relative importance to the second bit of the first word, and the first bit of the second word has a higher relative importance to the second bit of the second word.