Host load based dynamic storage system for configuration for increased performance
A data storage device including, in one implementation, a non-volatile memory device including a memory block that includes a plurality of memory dies and a controller that is coupled to the non-volatile memory device and that allocates power to non-memory components based on a determined usage of the memory dies. The controller is configured to monitor a utilization of the plurality of memory dies, determine a utilization state of the plurality of memory dies, and calculate an amount of available power allocated to the plurality of memory dies in response to determining that the plurality of memory dies are in a low utilization state. The controller is also configured to determine whether the amount of available power is above a predetermined threshold, and reallocate the available power to one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold.
1. A data storage device, comprising:
a non-volatile memory device including a memory block, the memory block including a plurality of memory dies; and
a controller coupled to the non-volatile memory device and configured to:
monitor a utilization of the plurality of memory dies;
determine whether the plurality of memory dies are in a high utilization state,
calculate an amount of available power allocated to the plurality of memory dies in response to determining that the plurality of memory dies are not in the high utilization state,
determine whether the amount of available power is above a predetermined threshold, and
reallocate the calculated available power to one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold.
2. The data storage device of claim 1 , wherein the controller is further configured to continue with an existing power allocation profile in response to determining that the plurality of memory dies are in the high utilization state.
3. The data storage device of claim 1 , wherein the controller is further configured to allocate maximum power to the plurality of memory dies in response to determining that the amount of available power is not above the predetermined threshold.
4. The data storage device of claim 1 , wherein the controller is configured to determine whether the plurality of memory dies are not in the high utilization state based on a predetermined percentage of the plurality of memory dies being idle.
5. The data storage device of claim 1 , wherein the controller is configured to determine whether the plurality of memory dies are not in the high utilization state based on a number of active memory dies that is less than or equal to a number of queued commands received from a host device.
6. The data storage device of claim 1 , wherein, to reallocate the available power to the one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold, the controller is further configured to reallocate power to a processor of the controller to increase operating frequency of the processor.
7. The data storage device of claim 1 , wherein, to reallocate the available power to the one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold, the controller is further configured to reallocate the available power to a toggle mode circuit to increase a data throughput of the data storage device.
8. The data storage device of claim 7 , wherein the controller is further configured to:
reduce a sense time of the plurality of memory dies, and
reallocate the available power to a low-density parity check circuit.
9. A method performed by data storage device having a controller coupled to a non-volatile memory device, the method comprising:
monitoring a utilization of a plurality of memory dies of the non-volatile memory device;
determining whether the plurality of memory dies are in a high utilization state;
calculating an amount of available power allocated to the plurality of memory dies in response to determining that the plurality of memory dies are not in the high utilization state;
determining whether the amount of available power is above a predetermined threshold; and
reallocating the available power to one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold.
10. The method of claim 9 , wherein determining whether the plurality of memory dies are not in the high utilization state is based on a predetermined percentage of the plurality of memory dies are idle.
11. The method of claim 9 , wherein determining whether the plurality of memory dies are not in the high utilization state is based on a number of active memory dies that is less than or equal to a number of queued commands received from a host device.
12. The method of claim 9 , wherein reallocating the available power to the one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold further includes reallocating power to a processor of the controller to increase operating frequency of the processor.
13. The method of claim 9 , wherein reallocating the available power to the one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold further includes reallocating the available power to a toggle mode circuit to increase a data throughput of the data storage device.
14. The method of claim 9 , further comprising:
configuring the plurality of memory dies to reduce a sense time of the plurality of memory dies; and
reallocating the available power to a low-density parity check circuit.
15. An apparatus, comprising:
means for monitoring a utilization of a plurality of memory dies within a memory block of the apparatus;
means for determining whether the plurality of memory dies are in a high utilization state;
means for calculating an amount of available power allocated to the plurality of memory dies in response to determining that the plurality of memory dies are not in the high utilization state;
means for determining whether the amount of available power is above a predetermined threshold; and
means for reallocating the available power to one or more components within a data storage device in response to determining that the amount of available power is above the predetermined threshold.
16. The apparatus of claim 15 , wherein the means for determining whether the plurality of memory dies are not in the high utilization state based on a predetermined percentage of the plurality of memory dies being idle.
17. The apparatus of claim 15 , wherein the means for determining whether the plurality of memory dies are not in the high utilization state based on a number of active memory dies that is less than or equal to a number of queued commands received from a host device.
18. The apparatus of claim 15 , wherein the means for reallocating the available power to the one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold further includes reallocating power to a processor of the apparatus to increase operating frequency of the processor.
19. The apparatus of claim 15 , wherein the means for reallocating the available power to the one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold further includes reallocating the available power to a toggle mode circuit of the apparatus to increase a data throughput of the data storage device.
20. The apparatus of claim 15 , further comprising:
means for reducing the sense time of the plurality of memory dies; and
means for reallocating the available power to a low-density parity check circuit.