IP Library Granted Patent US 8,275,981
Granted Patent B2
US 8,275,981 · App. 12/508,528 · Granted Sep 25, 2012

Flash storage system and method for accessing a boot program

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,275,981
App. No.
12/508,528
Granted
Sep 25, 2012
Kind
B2
Abstract

A computing system includes a flash storage device that loads a boot program from a flash storage of the flash storage device to a random access memory of the flash storage device. A processor of the computing system then accesses the boot program from the random access memory and executes the boot program.

Claims (36)

1. A flash storage system for accessing a boot program for a computing system, the flash storage system comprising:

a flash storage;

a random access memory;

a flash controller coupled to the flash storage and the random access memory, the flash controller configured to load the boot program from the flash storage into the random access memory;

a first bus interface coupled in communication with the random access memory and the flash controller, wherein the first bus interface is configured to be coupled to a system bus of the computing system; and

a second bus interface coupled in communication with the flash controller, wherein the second bus interface is configured to be coupled to a communication bus of the computing system.

2. The flash storage system of claim 1 , wherein the flash controller is further configured to load the boot program from the flash storage into the random access memory in response to a start signal.

3. The flash storage system of claim 2 further configured to generate the start signal upon a power-on of the flash storage system.

4. The flash storage system of claim 1 further comprising an integrated circuit comprising the flash storage, the random access memory, and the flash controller.

5. The flash storage system of claim 1 , wherein the flash controller is further configured to load the boot program from the flash storage into the random access memory by performing a direct memory access.

6. The flash storage system of claim 1 further configured to generate a ready signal indicating the boot program is accessible from the random access memory.

7. The flash storage system of claim 1 , wherein the flash controller is further configured to load the boot program from the random access memory to a data memory external of the flash storage system and to generate a ready signal indicating the boot program is accessible from the data memory.

8. The flash storage system of claim 7 , wherein the flash controller is further configured to load the boot program from the random access memory to the data memory by performing a direct memory access.

9. A computing system, comprising:

a processor coupled to a system bus and a communication bus;

a data memory coupled to the processor via the system bus; and

a flash storage device coupled to the processor, the flash storage device comprising

a flash storage;

a random access memory;

a flash controller coupled to the flash storage and the random access memory, the flash controller configured to load the boot program from the flash storage into the random access memory;

a first bus interface coupled in communication with the random access memory and the flash controller, wherein the first bus interface is configured to be coupled to the system bus; and

a second bus interface coupled in communication with the flash controller, wherein the second bus interface is configured to be coupled to the communication bus.

10. The computing system of claim 9 , wherein the flash controller is further configured to load the boot program from the flash storage into the random access memory in response to a start signal.

11. The computing system of claim 9 , wherein the flash storage device is further configured to generate the start signal upon a power-on of the flash storage system.

12. The computing system of claim 9 , wherein the processor is further configured to generate the start signal upon a power-on of the computing system.

13. The computing system of claim 9 further comprising an integrated circuit comprising the flash storage, the random access memory, and the flash controller.

14. The computing system of claim 9 , wherein the flash controller is further configured to load the boot program from the flash storage into the random access memory by performing a direct memory access.

15. The computing system of claim 9 , wherein the flash controller is further configured to generate a ready signal indicating the boot program is accessible from the random access memory.

16. The computing system of claim 9 , wherein the flash controller is further configured to load the boot program from the random access memory into the data memory.

17. The computing system of claim 16 , wherein the processor is further configured to generate a ready signal indicating the boot program is accessible from the data memory.

18. A method of accessing a boot program in a computing system comprising a flash storage device, the method comprising:

receiving a start signal;

loading the boot program from a flash storage of the flash storage device to a random access memory of the flash storage device based on the start signal, wherein the boot program comprises a basic input-output system; and

generating a ready signal indicating the boot program is accessible in the random access memory.

19. The method of claim 18 further comprising loading the boot program into the flash storage.

20. The method of claim 18 further comprising loading the boot program into a data memory of the computing system.

Assignments (11)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2018
From: HGST TECHNOLOGIES SANTA ANA, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046174/0446 →
CHANGE OF NAME Recorded Jul 1, 2015
From: STEC, INC.
To: HGST TECHNOLOGIES SANTA ANA, INC.
Reel/Frame 036042/0390 →