IP Library Granted Patent US 11,139,277
Granted Patent B2
US 11,139,277 · App. 16/814,864 · Granted Oct 5, 2021

Semiconductor device including contact fingers on opposed surfaces

Inventors: Chien Te Chen (Taichung, TW); Cong Zhang (Shanghai, CN); Hsiang Ju Huang (Taichung, TW); Xuyi Yang (Shanghai, CN); Yu Ying Tan (Taichung, TW); Han-Shiao Chen (Taichung, TW)
Assignee: Western Digital Technologies, Inc.
H01L25/0657H01L21/561H01L21/565H01L23/3121H01L23/49811H01L24/16H01L24/48H01L25/18H01L25/50H01L2224/48091H01L2224/48106H01L2224/48145H01L2224/48227H01L2225/0651H01L2225/06506H01L2225/06517H01L2225/06548H01L2225/06562H01L2225/06582H01L2924/14511
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Quick Facts
Patent No.
US 11,139,277
App. No.
16/814,864
Granted
Oct 5, 2021
Kind
B2
Abstract

A land grid array semiconductor device is disclosed which is configured for removable insertion to and from a host device. The land grid array semiconductor device may include a first set of one or more contact fingers on the first surface of the land grid array semiconductor device, and a second set of one or more contact fingers on the second surface of the land grid array semiconductor device. In order to electrically couple the second set of one or more contact fingers, one or more electrical connectors may be provided physically extending between the second set of one or more contact fingers and at least one of the substrate and the at least one semiconductor die.

Claims (41)

1. A semiconductor device, comprising:

a substrate comprising first and second opposed surfaces;

a first set of one or more contact fingers on the first surface of the substrate;

a plurality of semiconductor dies mounted on the second surface of the substrate and electrically coupled to the substrate, the plurality of semiconductor dies comprising:

one or more flash memory dies, and

a controller die mounted in an area on the second surface of the substrate;

a molding compound encapsulating the plurality of semiconductor dies;

a second set of one or more contact fingers on a surface of the molding compound; and

one or more electrical connectors physically extending between the second set of one or more contact fingers and one or more of the substrate and the plurality of semiconductor dies;

wherein the first surface of the substrate is devoid of contact fingers from the first set of contact fingers in an area opposed to the area on the second surface of the substrate comprising the controller die.

2. The semiconductor device of claim 1 , wherein the one or more electrical connectors comprise a vertical wire.

3. The semiconductor device of claim 1 , wherein the one or more electrical connectors comprise a vertical column of conductive material.

4. The semiconductor device of claim 1 , wherein the one or more electrical connectors comprise one or more solder balls.

5. The semiconductor device of claim 1 , wherein the one or more electrical connectors extend between the second set of one or more contact fingers and an uppermost semiconductor die of the plurality of semiconductor dies.

6. The semiconductor device of claim 1 , wherein the one or more electrical connectors extend between the second set of one or more contact fingers and the substrate.

7. The semiconductor device of claim 1 , wherein the second set of one or more contact fingers comprise a plurality of contact fingers on two halves of the surface of the molding compound.

8. The semiconductor device of claim 1 , wherein the second set of one or more contact fingers comprise a plurality of contact fingers on one half of the surface of the molding compound.

9. A land grid array semiconductor device configured for removable insertion to and from a host device, the land grid array semiconductor device comprising:

a substrate;

at least one semiconductor die mounted on the substrate and electrically coupled to the substrate, each of the at least one semiconductor dies comprising a plurality of die bond pads;

a molding compound encapsulating the at least one semiconductor die;

a surface of the substrate and a surface of the molding compound defining first and second opposed major surfaces of the land grid array semiconductor device;

a first set of one or more contact fingers on the first surface of the land grid array semiconductor device and electrically coupled to the substrate;

a second set of one or more contact fingers on the second surface of the land grid array semiconductor device; and

a plurality of bond wires electrically coupling the at least one semiconductor die to the substrate, a set of one or more bond wires of the plurality of bond wires further electrically coupling the second set of one or more contact fingers and one or more of the die bond pads on a semiconductor die of the at least one semiconductor die.

10. The semiconductor device of claim 9 , wherein the land grid array semiconductor device is configured according to one of the SD card, Nano card, Multimedia card and SIM card standards.

11. The semiconductor device of claim 9 , wherein the land grid array semiconductor device is configured according to one of the SD and the peripheral component interconnect express bus standards.

12. The semiconductor device of claim 9 , wherein the land grid array semiconductor device is configured according to one of the SD card, Nano card, Multimedia card and SIM card standards.

13. The semiconductor device of claim 9 , wherein the set of one or more bond wires extend between the second set of one or more contact fingers and the die bond pads of an uppermost semiconductor die of the at least one semiconductor die.

14. The semiconductor device of claim 9 , further comprising one or more electrical connectors extending between the second set of one or more contact fingers and the substrate.

15. The semiconductor device of claim 9 , wherein the at least one semiconductor die comprises a controller die mounted in an area on a first surface of the substrate, and wherein the first surface of the land grid array semiconductor device is devoid of contact fingers from the first set of contact fingers in an area opposed to the area on the first surface of the substrate comprising the controller die.

16. A land grid array semiconductor device configured for removable insertion to and from a host device, the land grid array semiconductor device comprising:

a substrate comprising first and second opposed surfaces;

a first set of contact finger means, on a first surface of the land grid array semiconductor device, for interfacing with pins of the host device;

a plurality of semiconductor dies mounted on the second surface of the substrate and electrically coupled to the substrate, the plurality of semiconductor dies comprising:

one or more flash memory dies, and

a controller die mounted in an area on the second surface of the substrate;

a molding compound encapsulating the plurality of semiconductor dies;

a second set of contact finger means, on a surface of the molding compound defining a second surface of the land grid array semiconductor device, for interfacing with pins of the host device; and

electrical connector means, physically extending between the second set of one or more contact fingers and one or more of the substrate and the plurality of semiconductor dies, for electrically connecting the second set of contact finger means within the land grid array semiconductor device;

wherein the first surface of the substrate is devoid of contact fingers from the first set of contact fingers in an area opposed to the area on the second surface of the substrate comprising the controller die.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053482 FRAME 0453 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0279 →
SECURITY INTEREST Recorded May 14, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053482/0453 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2020
From: CHEN, CHIEN TE; ZHANG, CONG; HUANG, HSIANG JU; YANG, XUYI; TAN, YU YING; CHEN, HAN-SHIAO
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052074/0034 →