IP Library Granted Patent US 11,714,565
Granted Patent B2
US 11,714,565 · App. 17/530,056 · Granted Aug 1, 2023

Block budget enhancement mechanisms for memory

Inventors: Bhanushankar Doni (Bangalore, IN); Raghavendra Gopalkrishnan (Bengaluru, IN)
Assignee: Western Digital Technologies, Inc.
G06F3/064G06F3/0619G06F3/0631G06F3/0659G06F3/0679
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Quick Facts
Patent No.
US 11,714,565
App. No.
17/530,056
Granted
Aug 1, 2023
Kind
B2
Abstract

A data storage device, in one implementation, includes a memory device having Single Level Cell (SLC) blocks and Multi-Level Cell (MLC) blocks, such as Triple Level Cell (TLC) blocks. If a SLC block is determined to have errors, the SLC block is reallocated as a TLC block. In some implementations, the TLC block is used to store TLC cold data.

Claims (77)

1. A data storage device, comprising:

a non-volatile memory device including a plurality of memory blocks, wherein the plurality of memory blocks include a first group of memory blocks and a second group of memory blocks that is separate from the first group of memory blocks; and

a controller coupled to the non-volatile memory device and configured to:

receive data from an external electronic device,

determine whether there is a sufficient number of memory blocks in the first group of memory blocks,

write the data to the first group of memory blocks in response to determining that there is the sufficient number of the memory blocks in the first group of memory blocks,

detect a failure in a first memory block of the first group of memory blocks,

transfer a portion of the data from the first memory block of the first group of memory blocks to a first memory block of the second group of memory blocks,

reallocate the first memory block of the first group of memory blocks as a second memory block of the second group of memory blocks, and

reallocate the first memory block of the second group of memory blocks as the first memory block of the first group of memory blocks.

2. The data storage device of claim 1 , wherein the first group of memory blocks includes single level cell (SLC) memory blocks.

3. The data storage device of claim 2 , wherein the second group of memory blocks includes at least one of:

SLC memory blocks,

triple level cell (TLC) memory blocks, or

quad level cell (QLC) memory blocks.

4. The data storage device of claim 3 , wherein the first memory block of the first group of memory blocks is a first SLC memory block, the first memory block from the second group of memory blocks is a second SLC memory block, and the second memory block of the second group of memory blocks is a TLC memory block.

5. The data storage device of claim 4 , wherein the controller is further configured to:

determine whether a maximum number of SLC memory blocks in the second group of memory blocks have been reallocated to the first group of memory blocks,

responsive to determining that the maximum number of SLC memory blocks in the second group of memory blocks have been reallocated to the first group of memory blocks, perform a folding operation on the first group of memory blocks from the SLC memory blocks to the TLC memory blocks;

detect a second failure in a third memory block during the folding operation, wherein the third memory block is from the second group of memory blocks;

responsive to detecting the second failure in the third memory block, transfer second data from the third memory block to a fourth memory block of the second group of memory blocks; and

responsive to transferring the second data from the third memory block to the fourth memory block, retire the third memory block.

6. The data storage device of claim 1 , wherein, to detect the failure in the first memory block of the first group of memory blocks, the controller is further configured to perform an enhanced post write read (EPWR) operation.

7. The data storage device of claim 1 , wherein the controller is further configured to:

responsive to detecting the failure in the first memory block of the first group of memory blocks, determine whether there is a hot memory block available in the second group of memory blocks, and

responsive to determining that the hot memory block is available in the second group of memory blocks, transfer the portion of the data from the first memory block to the hot memory block.

8. The data storage device of claim 7 , wherein the controller is further configured to:

responsive to determining that the hot memory block is not available, transfer the portion of the data from the first memory block to a third memory block in the second group of memory blocks.

9. The data storage device of claim 1 , wherein the controller is further configured to:

determine whether a wear leveling operation for the second memory block of the second group of memory blocks is needed,

determine whether the second memory block of the second group of memory blocks has previously transferred a second portion of the data to a hot memory block,

responsive to determining that the second memory block has previously transferred the second portion of the data to the hot memory block, allocate the hot memory block for the wear leveling operation, and

responsive to allocating the second memory block for the wear leveling operation, transfer the second portion of the data from the second memory block to a fourth memory block of the second group of memory blocks.

10. The data storage device of claim 9 , wherein the controller is further configured to:

responsive to determining that the second memory block has not previously transferred the data to the hot memory block, allocate a fifth memory block of the second group of memory blocks for receiving the second portion of the data from the second memory block, and

responsive to allocating the fifth memory block of the second group of memory blocks for receiving the second portion of the data from the second memory block, transfer the second portion of the data from the second memory block to the fifth memory block of the second group of memory blocks.

11. A method comprising:

receiving, with a data storage controller, data from an external electronic device;

determining, with the data storage controller, whether there is a sufficient number of memory blocks in a first group of memory blocks stored in a non-volatile memory;

writing, with the data storage controller, the data to the first group of memory blocks in response to determining that there is the sufficient number of the memory blocks in the first group of memory blocks;

detecting, with the data storage controller, a failure in a first memory block of the first group of memory blocks,

transferring, with the data storage controller, a portion of the data from the first memory block of the first group of memory blocks to a first memory block of a second group of memory blocks that is separate from the first group of memory blocks stored in the non-volatile memory;

reallocating, with the data storage controller, the first memory block of the first group of memory blocks as a second memory block of the second group of memory blocks; and

reallocating, with the data storage controller, the first memory block of the second group of memory blocks as the first memory block of the first group of memory blocks.

12. The method of claim 11 , wherein the first group of memory blocks includes single level cell (SLC) memory blocks.

13. The method of claim 12 , wherein the second group of memory blocks includes at least one of:

SLC memory blocks,

triple level cell (TLC) memory blocks, or

quad level cell (QLC) memory blocks.

14. The method of claim 13 , wherein the first memory block of the first group of memory blocks is a first SLC memory block, the first memory block from the second group of memory blocks is a second SLC memory block, and the second memory block of the second group of memory blocks is a TLC memory block.

15. The method of claim 14 , further comprising:

determining whether a maximum number of SLC memory blocks in the second group of memory blocks have been reallocated to the first group of memory blocks;

responsive to determining that the maximum number of SLC memory blocks in the second group of memory blocks have been reallocated to the first group of memory blocks, performing a folding operation on the first group of memory blocks from the SLC memory blocks to the TLC memory blocks;

detecting a second failure in a third memory block during the folding operation, wherein the third memory block is from the second group of memory blocks;

responsive to detecting the second failure in the third memory block, transferring second data from the third memory block to a fourth memory block of the second group of memory blocks; and

responsive to transferring the second data from the third memory block to the fourth memory block, retiring the third memory block.

16. An apparatus comprising:

means for receiving data from an external electronic device;

means for determining whether there is a sufficient number of memory blocks in a first group of memory blocks stored in a non-volatile memory;

means for writing the data to the first group of memory blocks in response to determining that there is the sufficient number of the memory blocks in the first group of memory blocks;

means for detecting a failure in a first memory block of the first group of memory blocks;

means for transferring a portion of the data from the first memory block of the first group of memory blocks to a first memory block of a second group of memory blocks that is separate from the first group of memory blocks stored in the non-volatile memory;

means for reallocating the first memory block of the first group of memory blocks as a second memory block of the second group of memory blocks; and

means for reallocating the first memory block of the second group of memory blocks as the first memory block of the first group of memory blocks.

17. The apparatus of claim 16 , further comprising:

means for determining, responsive to detecting the failure in the first memory block of the first group of memory blocks, whether there is a hot memory block available in the second group of memory blocks, and

means for transferring, responsive to determining that the hot memory block is available in the second group of memory blocks, the portion of the data from the first memory block to the hot memory block.

18. The apparatus of claim 17 , further comprising:

means for transferring, responsive to determining that the hot memory block is not available, the portion of the data from the first memory block to a third memory block in the second group of memory blocks.

19. The apparatus of claim 16 , further comprising:

means for determining whether a wear leveling operation for the second memory block of the second group of memory blocks is needed;

means for determining whether the second memory block of the second group of memory blocks has previously transferred a second portion of the data to a hot memory block;

means for allocating, responsive to determining that the second memory block has previously transferred the second portion of the data to the hot memory block, the hot memory block for the wear leveling operation; and

means for transferring, responsive to allocating the second memory block for the wear leveling operation; the second portion of the data from the second memory block to a fourth memory block of the second group of memory blocks.

20. The apparatus of claim 19 , further comprising:

means for allocating, responsive to determining that the second memory block has not previously transferred the data to the hot memory block, a fifth memory block of the second group of memory blocks for receiving the second portion of the data from the second memory block; and

means for transferring, responsive to allocating the fifth memory block of the second group of memory blocks for receiving the second portion of the data from the second memory block, the second portion of the data from the second memory block to the fifth memory block of the second group of memory blocks.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2021
From: DONI, BHANUSHANKAR; GOPALKRISHNAN, RAGHAVENDRA
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058155/0720 →