System and method for lower page data recovery in a solid state drive
View Patent ↗In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller performs a method that efficiently resolves the lower page corruption problem. In one embodiment, the method selects programmed lower page(s) for which paired upper page(s) have not been programmed, reads data from those selected lower page(s), corrects the read data, and reprograms the read data into those lower page(s). Since the number of lower pages in this condition is typically low (e.g., several pages in a block with hundreds or thousands of pages), this is a much more efficient method than reprogramming the entire block. In another embodiment, a similar reprogramming method is applied as a data recovery scheme in situations in which only lower pages are programmed (e.g., SLC memory, MLC memory in SLC mode, etc.).
1. A solid-state storage system, including:
a non-volatile flash memory array including a plurality of memory blocks, each including a plurality of memory pages; and
a controller configured to:
determine whether a state of the storage system meets a pre-defined data integrity condition;
in response to determining that the state of the storage system meets the pre-defined data integrity condition, select a memory page from the plurality of memory blocks;
read data from the selected memory page;
apply error correction to the read data to generate corrected data; and
program the corrected data back to the selected memory page.
2. The solid-state storage system of claim 1 , wherein the state of the storage system includes a state of a memory page in a reference memory block.
3. The solid-state storage system of claim 2 , wherein the state of the memory page in the reference memory block comprises a failure bit rate.
4. The solid-state storage system of claim 3 , wherein the failure bit rate is used to approximate time lapsed since last programmed.
5. The solid-state storage system of claim 3 , wherein the failure bit rate is obtained from a scanning process.
6. The solid-state storage system of claim 1 , wherein the non-volatile flash memory array comprises multi-level memory (MLC) cells and the memory page is in a memory block that is lower-page only programmed.
7. The solid-state storage system of claim 1 , wherein the non-volatile flash memory array comprises single-level memory (SLC) cells.
8. The solid-state storage system of claim 1 , wherein the controller is configured to determine whether the state of the storage system meets the pre-defined condition to initiate data recovery as part of a startup sequence.
9. The solid-state storage system of claim 8 , wherein the state of the storage system includes a program-erase cycle count.
10. A method of preserving data integrity in a solid-state storage system that includes a non-volatile flash memory array including a plurality of memory blocks, each including a plurality of memory pages, the method including:
determining whether a state of the storage system meets a pre-defined data integrity condition;
in response to determining that the state of the storage system meets the pre-defined data integrity condition, selecting a memory page from the plurality of memory blocks;
reading data from the selected memory page;
applying error correction to the read data to generate corrected data; and
programming the corrected data back to the selected memory page.
11. The method of claim 10 , wherein the state of the storage system includes a state of a memory page in a reference memory block.
12. The method of claim 11 , wherein the state of the memory page in the reference memory block comprises a failure bit rate.
13. The method of claim 12 , wherein the failure bit rate is used to approximate time lapsed since last programmed.
14. The method of claim 12 , wherein the failure bit rate is obtained from a scanning process.
15. The method of claim 10 , wherein the non-volatile flash memory array comprises multi-level memory (MLC) cells and the memory page is in a memory block that is lower-page only programmed.
16. The method of claim 10 , wherein the non-volatile flash memory array comprises single-level memory (SLC) cells.
17. The method of claim 10 , wherein determining whether the state of the storage system meets the pre-defined condition to initiate data recovery is performed as part of a startup sequence.
18. The method of claim 17 , wherein the state of the storage system includes a program-erase cycle count.
19. The solid-state storage system of claim 1 , wherein the state of the storage system is based on a voltage reference drift measured in a reference page.
20. The method of claim 10 , wherein the state of the storage system is based on a voltage reference drift measured in a reference page.