IP Library Granted Patent US 10,290,346
Granted Patent B2
US 10,290,346 · App. 15/388,737 · Granted May 14, 2019

Method and apparatus for low-latency read of flash storage devices using fractional bits per cell

Inventors: Zvonimir Z. Bandic (San Jose, CA); Minghai Qin (San Jose, CA); Seung-Hwan Song (San Jose, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G11C11/5628G11C11/5642G11C16/0483
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Quick Facts
Patent No.
US 10,290,346
App. No.
15/388,737
Granted
May 14, 2019
Kind
B2
Abstract

Aspects of the disclosure provide a method and a data storage apparatus for storing fractional bits per cell with low-latency read per page. In various embodiments, the memory cells are configured to store a fractional number of bits per cell using a multi-page construction with reduced number of read per page as compared to a single page construction. The data storage apparatus store data in a plurality of non-volatile memory (NVM) cells configured to store information in a plurality of pages, wherein each of the NVM cells is programmable to one of L program states for representing a fractional number of bits. The data storage apparatus reads a first part of the data from a first page of the plurality of pages by applying M number of read voltages to the plurality of NVM cells, wherein the M number of read voltages is less than L−1 program states.

Claims (57)

1. A method of operating a solid state drive, the method comprising:

storing data in a plurality of non-volatile memory (NVM) cells configured to store information in a plurality of pages, wherein each of the NVM cells is programmable to one of L program states for representing a fractional number of bits; and

reading a first part of the data from a first page of the plurality of pages by applying M number of read voltages to the plurality of NVM cells, wherein the M number of read voltages is less than L−1 program states.

2. The method of claim 1 , further comprising:

reading a second part of the data from a second page of the plurality of pages by applying N number of read voltages to the plurality of NVM cells,

wherein the N number of read voltages is less than L−1 program states, and the M number of read voltages and the N number of read voltages are different in number.

3. The method of claim 2 , wherein the first part of the data corresponds to a first file, and the second part of the data corresponds to a second file that is distinct from the first file.

4. The method of claim 2 , further comprising:

reading a third part of the data from a third page of the plurality of pages by applying O number of read voltages to the plurality of NVM cells,

wherein the O number of read voltages is less than the L−1 program states, and at least two of the M number of read voltages, the N number of read voltages, and the O number of read voltages are different in number.

5. The method of claim 1 , further comprising:

reading different parts of the data from the respective pages of the plurality of pages by applying an average of N number of read voltages to the plurality of NVM cells, wherein the N number of read voltages is less than the L−1 program states.

6. The method of claim 1 , wherein the storing comprises:

storing the first part of the data in the first page; and

storing a second part of the data in a second page of the plurality of pages, wherein the first page is configured to store a greater quantity of different values than the second page.

7. The method of claim 1 , further comprising:

reading a second part of the data from a second page of the plurality of pages by applying N number of read voltages to the plurality of NVM cells,

wherein the N number of read voltages is less than the L−1 number of program states, and

wherein the read voltages of the first page are different from the read voltages of the second page.

8. The method of claim 1 , wherein the plurality of NVM cells comprise NAND flash memory cells.

9. The method of claim 1 , wherein the storing comprises storing the first part of the data in a region of the first page mapped to a plurality of first values.

10. A solid state data storage device comprising:

a controller; and

a plurality of non-volatile memory (NVM) cells operatively coupled to the controller,

wherein the controller is configured to:

store data in the plurality of NVM cells configured to store information in a plurality of pages, wherein each of the NVM cells is programmable to one of L program states for representing a fractional number of bits; and

read a first part of the data from a first page of the plurality of pages by applying M number of read voltages to the plurality of NVM cells, wherein the M number of read voltages is less than L−1 program states.

11. The solid state data storage device of claim 10 , wherein the controller is configured to:

read a second part of the data from a second page of the plurality of pages by applying N number of read voltages to the plurality of NVM cells,

wherein the N number of read voltages is less than L−1 program states, and the M number of read voltages and the N number of read voltages are different in number.

12. The solid state data storage device of claim 11 , wherein the controller is further configured to:

store the first part of the data to the first page of the NVM cells; and

store the second part of the data to the second page of the NVM cells,

wherein the first page is configured to store a greater quantity of different values than the second page.

13. The solid state data storage device of claim 12 , wherein the controller is further configured to:

set a first cell of the NVM cells to a first program level and a second cell of the NVM cells to a second program level, to store at least one of the first part of the data and the second part of the data.

14. A solid state data storage device comprising:

means for storing data in a plurality of non-volatile memory (NVM) cells configured to store information in a plurality of pages, wherein each of the NVM cells is programmable to one of L program states for representing a fractional number of bits; and

means for reading a first part of the data from a first page of the plurality of pages by applying M number of read voltages to the plurality of NVM cells, wherein the M number of read voltages is less than L−1 program states.

15. The solid state data storage device of claim 14 , further comprising:

means for reading a second part of the data from a second page of the plurality of pages by applying N number of read voltages to the plurality of NVM cells,

wherein the N number of read voltages is less than L−1 program states, and the M number of read voltages and the N number of read voltages are different in number.

16. The solid state data storage device of claim 15 , wherein the first part of the data corresponds to a first file, and the second part of the data corresponds to a second file that is distinct from the first file.

17. The solid state data storage device of claim 15 , further comprising:

means for reading a third part of the data from a third page of the plurality of pages by applying O number of read voltages to the plurality of NVM cells,

wherein the O number of read voltages is less than the L−1 program states, and at least two of the M number of read voltages, the N number of read voltages, and the O number of read voltages are different in number.

18. The solid state data storage device of claim 14 , further comprising:

means for reading different parts of the data from the respective pages of the plurality of pages by applying an average of N number of read voltages to the plurality of NVM cells, wherein the N number of read voltages is less than the L−1 program states.

19. The solid state data storage device of claim 14 , wherein the storing comprises:

means for storing the first part of the data in the first page; and

means for storing a second part of the data in a second page of the plurality of pages, wherein the first page is configured to store a greater quantity of different values than the second page.

20. The solid state data storage device of claim 14 , further comprising:

means for reading a second part of the data from a second page of the plurality of pages by applying N number of read voltages to the plurality of NVM cells,

wherein the N number of read voltages is less than the L−1 number of program states, and

wherein the read voltages of the first page are different from the read voltages of the second page.

21. The solid state data storage device of claim 14 , wherein the plurality of NVM cells comprise NAND flash memory cells.

22. The solid state data storage device of claim 14 , wherein the storing comprises storing the first part of the data in a region of the first page mapped to a plurality of first values.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2017
From: BANDIC, ZVONIMIR Z.; QIN, MINGHAI; SONG, SEUNG-HWAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 041001/0013 →
Continuity (1)
Related Publication 20180181301A1 · Jun 28, 2018