IP Library Granted Patent US 12,461,583
Granted Patent B2
US 12,461,583 · App. 18/455,958 · Granted Nov 4, 2025

PHY lanes disabling for power efficiency

Inventors: Amir Segev (Meiter, IL); Shay Benisty (Beer Sheva, IL)
Assignee: Sandisk Technologies, Inc.
G06F1/3253G06F13/4068
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Quick Facts
Patent No.
US 12,461,583
App. No.
18/455,958
Granted
Nov 4, 2025
Kind
B2
Abstract

Instead of entering lanes into an unused power state, enter unactive lanes into an unconnected power state to save more current during low power states. Using a small control logic will allow a controller to control unactive lanes in low power mode. When a lane is in an unactive power state or in an unused power state, an unactive lane controller (ULC) uses side-band signaling to place the unactive lane into either unused power state or unconnected power state. When a lane is in unused power state, then the ULC places the lane in unconnected power state. A single ULC is able to controller multiple lanes or you can have multiple ULC's, each controlling a single lane.

Claims (36)

1 . A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

determine that one or more lanes of a physical connection (PHY) is unused;

change a state of the one or more lanes of the PHY to an unconnected state from an unused state; and

change the state of the one or more lanes of the PHY back to the unused state, wherein the controller comprises a plurality of unactive lanes controllers (ULCs), wherein the one or more lanes comprises a plurality of lanes, and wherein a number of ULCs is equal to one less than a number of lanes of the plurality of lanes.

2 . The data storage device of claim 1 , further comprising:

a media access layer (MAC), wherein the plurality of the ULCs are coupled between the PHY and the MAC.

3 . The data storage device of claim 2 , wherein each ULC is configured to monitor a different link training and status state machine (LTSSM) link.

4 . The data storage device of claim 2 , wherein a first ULC of the plurality of ULCs is configured to cause at least one lane to always work in an unconnected power saving state.

5 . The data storage device of claim 2 , wherein a first ULC of the plurality of ULCs is configured to cause at least one lane to always work in an unused power saving state.

6 . The data storage device of claim 2 , wherein the plurality of ULCs are configured to work dynamically.

7 . The data storage device of claim 6 , wherein the plurality of ULCs are configured to collect information regarding power states of lanes of the PHY.

8 . The data storage device of claim 6 , wherein the plurality of ULCs are configured to receive external decision making information regarding power states of lanes of the PHY.

9 . A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller includes:

a physical connection (PHY) for connecting a plurality of lanes to a host device;

a media access layer (MAC) coupled to the PHY; and

at least one unactive lanes controller (ULC) coupled between the PHY and the MAC, wherein the at least one ULC is configured to move inactive lanes of the plurality of lanes into an unconnected state, wherein the at least one ULC comprises a plurality of ULCs and wherein a number of ULCs is equal to one less than a number of the plurality of lanes.

10 . The data storage device of claim 9 , wherein the at least one ULC is configured to detect a power state of the plurality of lanes.

11 . The data storage device of claim 9 , wherein the at least one ULC is configured to evaluate a preferred low power state of non-active lanes of the plurality of lanes based at least in part on a link training and status state machine (LTSSM) link.

12 . The data storage device of claim 9 , wherein the at least one ULC is configured to monitor an interface between the PHY and MAC and detect a power change for the plurality of lanes.

13 . The data storage device of claim 9 , wherein the at least one ULC is configured to wakeup a first lane of the plurality of lanes from the unconnected state and place the first lane into a MAC controlled state.

14 . The data storage device of claim 9 , wherein the at least one ULC is configured to predict when to change a state of at least one lane of the plurality of lanes.

15 . A data storage device, comprising:

means to store data; and

a controller coupled to the means to store data, wherein the controller is configured to:

monitor power states of one or more lanes connecting a physical connection (PHY) to a host device;

detect that one or more lanes is in an unused power state; and

change a power state of the one or more lanes in the unused power state to an unconnected power state, wherein the controller is configured to perform the monitoring at a location between the PHY and a media access layer (MAC), wherein the controller comprises a plurality of unactive lanes controllers (ULCs), wherein the one or more lanes comprises a plurality of lanes, and wherein a number of ULCs is equal to one less than a number of lanes of the plurality of lanes.

16 . The data storage device of claim 15 , wherein the controller is configured to predict when the one or more lanes is to return to an active power state.

17 . The data storage device of claim 16 , wherein the predicting is a time based predicting.

18 . The data storage device of claim 15 , wherein each ULC is configured to monitor a different link training and status state machine (LTSSM) link.

19 . The data storage device of claim 15 , wherein a first ULC of the plurality of ULCs is configured to cause at least one lane to always work in an unconnected power saving state.

20 . The data storage device of claim 15 , wherein a first ULC of the plurality of ULCs is configured to cause at least one lane to always work in an unused power saving state.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2023
From: SEGEV, AMIR; BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 064901/0844 →
Continuity (1)
Related Publication 20250068226A1 · Feb 27, 2025
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