Technologies for partial link width states for multilane links
Systems and devices can include an upstream port, a downstream port, and a multilane link connecting the upstream port to the downstream port, the multilane link comprising a first link width. The upstream port or the downstream port can be configured to determine that the downstream port is to operate using a second link width, the second link width less than the first link width; transmit to the upstream port an indication of a last data block for the first link width across one or more lanes of the multilane link; cause a first set lanes to enter an idle state; and transmit data on a second set of lanes, the second set of lanes defining the second link width.
1. An apparatus comprising:
a port to couple to a device over a link, the link comprising a set of lanes, the set of lanes comprising a total number of lanes, a first number of lanes less than the total number of lanes, and a second number of lanes less than the total number of lanes; the port to:
transmit data on the link using each lane of the set of lanes;
receive a request to transmit data on the first number of lanes;
transmit an electrical idle ordered set (EIOS) on the second number of lanes during a SKP OS interval; and
transmit skip ordered sets (SKP OS) on the first number of lanes during the SKP OS interval; and
transmit data on the first number of lanes.
2. The apparatus of claim 1 , the port to send an acknowledgment message across the link acknowledging the request to transmit data using the first number of lanes.
3. The apparatus of claim 1 , wherein the first number of lanes is greater than the second number of lanes; the port to:
send a request across the link to transmit data using the second number of lanes; and
send an acknowledgment message across the link acknowledging the request to transmit data using the first number of lanes.
4. The apparatus of claim 1 , the port to receive a request to transmit data on a third number of lanes, the third number lanes adding additional lanes to the first number of lanes.
5. The apparatus of claim 1 , where the port is to:
receive a request to up-size link width from the first number of lanes to the total number of lanes;
transmit training set ordered sets on the second number of lanes in response to receipt of the request to up-size the link width and contemporaneously transmit data on the first number of lines;
transmit SKP OS on the total number of lanes after transmission of the training ordered sets; and
transmit data on the total number of lanes after the transmission of the SKP OS on the total number of lanes.
6. The apparatus of claim 4 , the port to:
transmit data on the first number of lanes;
transmit an electrical idle exit ordered set (EIEOS) on the additional lanes;
transmit training sequences on the additional lanes; and
transmit data on the third number of lanes.
7. A method comprising:
transmitting data across a multilane link using an active link state (L0 state), the active link state using each lane of the multilane link,
the multilane link comprising a first subset of lanes and a second subset of lanes;
receiving a request to transmit data using a partial link width state (L0p state), the request indicating the first subset of lanes for transmission of data;
transmitting an electrical idle ordered set (EIOS) on the second subset of lanes during a skip ordered set (SKP OS) interval;
deactivating the second subset of lanes; and
transmitting data on the first subset of lanes.
8. The method of claim 7 , further comprising sending an acknowledgment message acknowledging the request.
9. The method of claim 7 , further comprising transmitting skip ordered sets (SKP OS) on the first subset of lanes during the SKP OS interval.
10. The method of claim 7 , wherein the first subset of lanes is greater than the second subset of lanes, the method further comprising:
sending a request to transmit data using the LOp state, the request indicating the second subset of lanes for transmission of data; and
sending an acknowledgment message across the link acknowledging the request to transmit data using the first subset of lanes.
11. The method of claim 7 , further comprising receiving a request to transmit data on a third subset of lanes, the third subset of lanes adding additional lanes to the first subset of lanes.
12. The method of claim 7 , further comprising:
receiving a request to up-size link width from the first subset of lanes to the first and second subsets of lanes;
transmitting training set ordered sets on the second subset of lanes in response to receipt of the request to up-size the link width and contemporaneously transmitting data on the first subset of lines;
transmitting skip ordered sets (SKP OS) on the first and second subsets of lanes after transmission of the training ordered sets; and
transmitting data on the first and second subsets of lanes after the transmission of the SKP OS on the first and second subsets of lanes.
13. The method of claim 11 , further comprising:
transmitting data on the first subset of lanes;
transmitting an electrical idle exit ordered set (EIEOS) on the additional lanes;
transmitting training sequences on the additional lanes; and
transmitting data on the third subset of lanes.
14. A system comprising:
a first component comprising a downstream port (DSP);
a second component comprising an upstream port (USP);
a multilane link interconnecting the DSP and the USP, the multilane link comprising a total number of lanes, the total number of lanes comprising a first number of lanes and a second number of lanes;
the DSP to:
transmit data on the link using each lane of the total number of lanes;
receive, from the USP, a request to reduce a number of active lanes from the total number of lanes to the first number of lanes;
during a skip ordered set (SKP OS) interval:
send an electrical idle ordered set (EIOS) to the USP instead of a SKP OS on the second number of lanes, and
send a SKP OS on the first number of lanes to the USP; and
after the SKP OS interval, send data on the first number of lanes to the USP, the first number of lanes less than the total number of lanes.
15. The system of claim 14 , the DSP to send an acknowledgment message acknowledging the request to the USP.
16. The system of claim 14 , wherein the first number of lanes is greater than the second number of lanes;
the DSP to:
send a request to the USP to transmit data using the second number of lanes; and
send an acknowledgment message to the USP acknowledging the request to transmit data using the first number of lanes.
17. The system of claim 14 , the DSP to:
send the EIOS to the USP on the second number of lanes during the SKP OS interval; and
send the SKP OS to the USP on the first number of lanes during a SKP OS interval.
18. The system of claim 14 , the DSP to receive a request from the USP to transmit data on a third number of lanes, the third number of lanes adding additional lanes to the first number of lanes.
19. The system of claim 14 , wherein the DSP is to transmit data using each lane of the total number of lanes during an active link state.
20. The system of claim 14 , wherein the DSP is to transmit data using the first number of lanes during a partial link width state.
21. The system of claim 14 , where the DSP is to:
receive a request to up-size link width from the first number of lanes to the total number of lanes;
transmit training set ordered sets on the second number of lanes in response to receipt of the request to up-size the link width and contemporaneously transmit data on the first number of lines;
transmit skip ordered sets on the total number of lanes after transmission of the training ordered sets; and
transmit data on the total number of lanes after the transmission of the skip ordered sets on the total number of lanes.
22. The system of claim 18 , the DSP to:
transmit data to the USP on the first number of lanes;
transmit an electrical idle exit ordered set (EIEOS) to the USP on the additional lanes;
transmit training sequences to the USP on the additional lanes; and
transmit data to the USP on the third number of lanes.