Controlling partial link width states for multilane links

1. An apparatus comprising:

a port; and

a multilane link coupled to the port, the multilane link operating at a first link width;

the port comprising hardware circuitry to:

determine that the port is to operate using a second link width, the second link width less than the first link width;

transmit an indication of a last data block for the first link width across one or more lanes of the multilane link;

cause a first set lanes to enter an idle state; and

transmit data on a second set of lanes, the second set of lanes defining the second link width;

transmit an indication to a link partner to activate a third set of lanes;

perform link training on the third set of lanes while transmitting data on the second set of lanes;

transmit an end data stream on the second set of lanes; and

transmit data on the second and third set of lanes.

2. The apparatus of claim 1 , the port to, prior to transmitting the indication of a last data block for a first link width:

transmit across one or more of the first number of lanes a request to transition to the second link width;

receive from a link partner across one or more lanes of the multilane link an acknowledgement to transition to the second link width.

3. The apparatus of claim 1 , wherein the indication of the last data block is provided in a last double word of a data block using the first link width.

4. The apparatus of claim 1 , the port to:

transmit an electric idle ordered set on the first set of lanes; and

transmit skip ordered set (SKP OS) on the second set of lanes.

5. The apparatus of claim 1 , wherein the port is a downstream port, the port to:

receive, from an upstream port across the multilane link, a request to transition from the first link width to a third link width, the third link width less than the first link width and different from the second link width;

ignore the request; and

cause the link to transition to the second link width upon receiving an acknowledgement from the upstream port that the upstream port can transition to the second link width.

6. The apparatus of claim 1 , the port to:

transmit and receive first training sequence ordered sets (TS1 OS) to link train the third set of lanes; and

transmit and receive second training sequence ordered sets (TS2 OS) that indicate that link training is complete on the third set of lanes.

7. The apparatus of claim 3 , wherein the last double word comprises an indication of the second link width.

8. The apparatus of claim 6 , the port to:

perform lane deskew on the third set of lanes; and

transmit start data stream on transmission lanes that include lanes from the second and third sets of lanes.

9. A method performed by a port coupled to a multilane link, the multilane link comprising a first link width, the method comprising:

determining that a port of a multilane link is to operate using a second link width, the second link width less than the first link width;

transmitting an indication of a last data block for the first link width across one or more lanes of the multilane link;

causing a first set lanes to enter an idle state; and

transmitting data on a second set of lanes, the second set of lanes defining the second link width;

transmitting an indication to a link partner to activate a third set of lanes;

performing link training on the third set of lanes while transmitting data on the second set of lanes;

transmitting an end data stream on the second set of lanes; and

transmitting data on the second and third set of lanes.

10. The method of claim 9 , comprising, prior to transmitting the indication of a last data block for a first link width:

transmitting across one or more of the first number of lanes a request to transition to the second link width;

receiving from a link partner across one or more lanes of the multilane link an acknowledgement to transition to the second link width.

11. The method of claim 9 , wherein the indication of the last data block is provided in a last double word of a data block using the first link width.

12. The method of claim 9 , further comprising:

transmitting an electric idle ordered set (EIOS) on the first set of lanes; and

transmitting skip ordered set SKP OS on the second set of lanes.

13. The method of claim 9 , wherein the port is a downstream port, the method comprising:

receiving, from an upstream port across the multilane link, a request to transition from the first link width to a third link width, the third link width less than the first link width and different from the second link width;

ignoring the request; and

causing the link to transition to the second link width upon receiving an acknowledgement from the upstream port that the upstream port can transition to the second link width.

14. The method of claim 9 , further comprising:

transmitting and receive first training sequence ordered sets (TS1 OS) to link train the third set of lanes; and

transmitting and receive second training sequence ordered sets (TS2 OS) that indicate that link training is complete on the third set of lanes.

15. The method of claim 11 , wherein the last double word comprises an indication of the second link width.

16. The method of claim 14 , further comprising:

performing lane deskew on the third set of lanes; and

transmitting start data stream on transmission lanes that include lanes from the second and third sets of lanes.

17. A non-transitory computer-readable medium having program instructions stored therein, wherein the program instructions are executable by a computer system to perform operations comprising:

determining that the port is to operate using a second link width, the second link width less than the first link width;

transmitting an indication of a last data block for the first link width across one or more lanes of the multilane link;

causing a first set lanes to enter an idle state; and

transmitting data on a second set of lanes, the second set of lanes defining the second link width;

transmitting an indication to a link partner to activate a third set of lanes;

performing link training on the third set of lanes while transmitting data on the second set of lanes;

transmitting an end data stream on the second set of lanes; and

transmitting data on the second and third set of lanes.

18. The non-transitory computer-readable medium of claim 17 , the operations further comprising:

prior to transmitting the indication of a last data block for a first link width:

transmitting across one or more of the first number of lanes a request to transition to the second link width;

receiving from a link partner across one or more lanes of the multilane link an acknowledgement to transition to the second link width.

19. The non-transitory computer-readable medium of claim 17 , wherein the indication of the last data block is provided in a last double word of a data block using the first link width.

20. The non-transitory computer-readable medium of claim 17 , the operations further comprising:

transmitting an electric idle ordered set (EIOS) on the first set of lanes; and

transmitting skip ordered set SKP OS on the second set of lanes.

21. The non-transitory computer-readable medium of claim 17 , the operations further comprising:

transmitting and receive first training sequence ordered sets (TS1 OS) to link train the third set of lanes; and

transmitting and receive second training sequence ordered sets (TS2 OS) that indicate that link training is complete on the third set of lanes.

22. The non-transitory computer-readable medium of claim 19 , wherein the last double word comprises an indication of the second link width.

23. A system comprising:

an upstream port;

a downstream port; and

a multilane link connecting the upstream port to the downstream port, the multilane link comprising a first link width; the downstream port to:

determine that the downstream port is to operate using a second link width, the second link width less than the first link width;

transmit to the upstream port an indication of a last data block for the first link width across one or more lanes of the multilane link;

cause a first set lanes to enter an idle state; and

transmit data on a second set of lanes, the second set of lanes defining the second link width;

transmit an indication to a link partner to activate a third set of lanes;

perform link training on the third set of lanes while transmitting data on the second set of lanes;

transmit an end data stream on the second set of lanes; and

transmit data on the second and third set of lanes.

24. The system of claim 23 , the downstream port to, prior to transmitting the indication of a last data block for a first link width:

transmit across one or more of the first number of lanes a request to transition to the second link width;

receive from the upstream port across one or more lanes of the multilane link an acknowledgement (ACK) to transition to the second link width.

25. The system of claim 23 , wherein the indication of the last data block is provided in a last double word of a data block using the first link width.

26. The system of claim 23 , the port to:

transmit an electric idle ordered set (EIOS) on the first set of lanes; and

transmit skip ordered set (SKP OS) on the second set of lanes.

27. The system of claim 23 , the downstream port to:

receive, from the upstream port across the multilane link, a request to transition from the first link width to a third link width, the third link width less than the first link width and different from the second link width;

ignore the request; and

cause the link to transition to the second link width upon receiving an acknowledgement from the upstream port that the upstream port can transition to the second link width.

28. The system of claim 23 , the downstream port to:

transmit and receive first training sequence ordered sets (TS1 OS) to link train the third set of lanes; and

transmit and receive second training sequence ordered sets (TS2 OS) that indicate that link training is complete on the third set of lanes.

29. The apparatus of claim 25 , wherein the last double word comprises an indication of the second link width.

30. The system of claim 28 , the downstream port to:

perform lane deskew on the third set of lanes; and

transmit start data stream on transmission lanes that include lanes from the second and third sets of lanes.