IP Library Granted Patent US 12,360,677
Granted Patent B2
US 12,360,677 · App. 18/485,050 · Granted Jul 15, 2025

Erase type detection mechanism

Inventors: YunKyu Lee (SeongNam, KR); SangYun Jung (YongIn, KR); Minyoung Kim (Suwon, KR); SeungBeom Seo (Seoul, KR); MinWoo Lee (Hwasung, KR)
Assignee: Sandisk Technologies, Inc.
G06F3/0616G06F3/064G06F3/0652G06F3/0659G06F3/0679G11C16/3445
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Quick Facts
Patent No.
US 12,360,677
App. No.
18/485,050
Granted
Jul 15, 2025
Kind
B2
Abstract

Aspects of a storage device are provided for handling detection and operations associated with an erase block type of the block. The storage device includes one or more non-volatile memories each including a block, and one or more controllers operable to cause the storage device to perform erase type detection and associated operations for single blocks or metablocks. For instance, the controller(s) may erase the block prior to a power loss event, perform at least one read of the block following the power loss event, identify the erase block type of the block in response to the at least one read, and program the block based on the identified erase block type without performing a subsequent erase prior to the program. The controller(s) may also perform metablock operations associated with the identified erase block type. Thus, unnecessary erase operations during recovery from an ungraceful shutdown (UGSD) may be mitigated.

Claims (62)

1. A method for handling detection and operations associated with a metablock that includes a plurality of blocks in one or more non-volatile memories of a storage device following erasure of at least one of the plurality of blocks prior to a power loss event, the method comprising:

performing at least one read of a page in each block included in the metablock following the power loss event;

identifying, based on the at least one read, an erase block type of each block included in the metablock based on a number of bits read from the page in each block and one or more bit count thresholds, wherein at least one of the plurality of blocks is identified as a multi-level cell (MLC) erase block type; and

performing a metablock operation associated with the erase block type without erasing the metablock prior to the metablock operation in response to the identified erase block type being same for each of the blocks.

2. The method of claim 1 , wherein the at least one read of the page in each block is an MLC read of the page, and wherein the method further comprises:

determining whether a number of bits corresponding to an MLC erase state which are read from the page is less than a bit count threshold, wherein the at least one of the plurality of blocks is identified as the MLC erase block type

in response to the number of bits being less than the bit count threshold.

3. The method of claim 1 , wherein the metablock is a first metablock, and wherein the method further comprises:

performing an MLC read of a first page of a first block of a second metablock;

determining whether a first number of bits corresponding to an erase state which are read from the first page is greater than or equal to a first bit count threshold;

performing a single-level cell (SLC) read of the first page of the first block in response to the first number of bits being greater than or equal to the first bit count threshold when performing the at least one read of the first block;

determining whether a second number of bits corresponding to an SLC erase state which are read from the first page is less than a second bit count threshold; and

identifying the erase block type to be SLC in response to the second number of bits being less than the second bit count threshold.

4. The method of claim 1 , wherein

determining whether at least one of the blocks is an erase aborted block;

erasing, prior to performing the metablock operation, the erase aborted block based on the identified erase block type without subsequently programming and re-erasing the erase aborted block.

5. The method of claim 1 , wherein the metablock is a first metablock, and wherein the method further comprises:

performing the at least one read of a first page in a first block included in a second metablock;

identifying the erase block type of the first block based on a number of bits read from the first page and one or more bit count thresholds;

determining that a second block of the second metablock is not the same erase block type as the first block;

erasing, without subsequently programming and re-erasing the first block, the first block based on the first block being a different erase block type relative to the second block; and

perform a metablock operation associated with the second block after the erase of the first block.

6. The method of claim 5 , wherein the identified erase block type of the first block is single-level cell (SLC), and the different erase block type of the second block is multi-level cell (MLC).

7. The method of claim 1 , wherein the one or more blocks are initially associated with an initial erase block type, and the method further comprises:

changing an association from the initial erase block type to the erase block type prior to the power loss event.

8. The method of claim 1 , wherein the power loss event is an ungraceful shutdown (UGSD) of the storage device.

9. A storage device, comprising:

one or more non-volatile memories comprising a metablock that includes a plurality of blocks; and

means for handling detection and operations associated with the metablock following erasure of at least one of the plurality of blocks prior to a power loss event, the means for handling being configured to:

perform at least one read of a page in each block included in the metablock following the power loss event;

identify, based on the at least one read, an erase block type of each block included in the metablock based on a number of bits read from the page in each block and one or more bit count thresholds, wherein at least one of the plurality of blocks is identified as a multi-level cell (MLC) erase block type; and

perform a metablock operation associated with the erase block type without erasing the metablock prior to the metablock operation in response to the identified erase block type being same for each of the blocks.

10. The storage device of claim 9 , wherein the one or more blocks are initially associated with an initial erase block type, and the means for handling is further configured to:

change an association from the initial erase block type to the erase block type prior to the power loss event.

11. A storage device, comprising:

one or more non-volatile memories comprising a metablock that includes a plurality of blocks; and

one or more controllers each communicatively coupled with at least one of the one or more non-volatile memories, the one or more controllers, individually or in any combination, operable to cause the storage device to:

erase one or more blocks of the plurality of blocks prior to a power loss event, wherein each of the plurality of blocks is associated with an erase block type;

perform at least one read of a page in each block included in the metablock following the power loss event;

identify, based on the at least one read, the erase block type of each block included in the metablock based on a number of bits read from the page in each block and one or more bit count thresholds, wherein at least one of the plurality of blocks is identified as a multi-level cell (MLC) erase block type; and

perform a metablock operation associated with the erase block type without erasing the metablock prior to the metablock operation in response to the identified erase block type being same for each of the blocks.

12. The storage device of claim 11 , wherein the at least one read of the page in each block is an MLC read of the page, and wherein the one or more controllers, individually or in combination, are further operable to cause the storage device to:

determine whether a number of bits corresponding to an MLC erase state which are read from the page is less than a bit count threshold, wherein the at least one of the plurality of blocks is identified as the MLC erase block type in response to the number of bits being less than the bit count threshold.

13. The storage device of claim 11 , wherein the metablock is a first metablock, and wherein the one or more controllers, individually or in combination, are further operable to cause the storage device to:

perform an MLC read of a first page of a first block of a second metablock;

determine whether a first number of bits corresponding to an erase state which are read from the first page is greater than or equal to a first bit count threshold;

perform a single-level cell (SLC) read of the first page of the first block in response to the first number of bits being greater than or equal to the first bit count threshold when performing the at least one read of the first block;

determine whether a second number of bits corresponding to an SLC erase state which are read from the first page is less than a second bit count threshold; and

identify the erase block type to be SLC in response to the second number of bits being less than the second bit count threshold.

14. The storage device of claim 11 , wherein the one or more controllers, individually or in combination, are further operable to cause the storage device to:

determine whether at least one of the blocks is an erase aborted block;

erase, prior to performing the metablock operation, the erase aborted block based on the identified erase block type without subsequently programming and re-erasing the erase aborted block.

15. The storage device of claim 11 , wherein the metablock is a first metablock, and wherein the one or more controllers, individually or in combination, are further operable to cause the storage device to:

perform the at least one read of a first page in a first block included in a second metablock;

identify the erase block type of the first block based on a number of bits read from the first page and one or more bit count thresholds;

determine that a second block of the second metablock is not the same erase block type as the first block;

erase, without subsequently programming and re-erasing the first block, the first block based on the first block being a different erase block type relative to the second block; and

perform a metablock operation associated with the second block after the erase of the first block.

16. The storage device of claim 15 , wherein the identified erase block type of the first block is single-level cell (SLC), and the different erase block type of the second block is multi-level cell (MLC).

17. The storage device of claim 11 , wherein the one or more blocks are initially associated with an initial erase block type, and the one or more controllers, individually or in combination, are further operable to cause the storage device to:

change an association from the initial erase block type to the erase block type prior to the power loss event.

18. The storage device of claim 11 , wherein the power loss event is an ungraceful shutdown (UGSD) of the storage device.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2023
From: LEE, YUNKYU; JUNG, SANGYUN; KIM, MINYOUNG; SEO, SEUNGBEOM; LEE, MINWOO
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 065874/0367 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
Continuity (1)
Related Publication 20250123751A1 · Apr 17, 2025
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