Memory block erase protocol

1. A system comprising:

a memory device comprising a memory array, the memory array comprising a plurality of memory cells; and

a processing device coupled to the memory device, the processing device to perform operations comprising:

determining a value of a metric associated with a program-erase cycle (PEC) of one or more memory blocks of the memory array, wherein the memory array further comprises a plurality of memory blocks, and wherein a first memory block comprises a first set of memory cells of the plurality of memory cells;

responsive to determining that the value of the metric is below a predetermined threshold, initiating an erase protocol of the memory device;

erasing less than a predetermined portion of free sets of memory cells associated with one or more free memory blocks of the plurality of memory blocks;

subsequent to erasing less than the predetermined portion of free sets of memory cells, receiving a programming command directed to the first set of memory cells; and

performing a programming operation with respect to the first set of memory cells responsive to receiving the programming command.

2. The system of claim 1 , wherein the operations further comprise:

determining, responsive to initiating the erase protocol, an amount of free memory blocks comprising sets of free memory cells of the plurality of memory cells; and

erasing memory cells of a portion of the free memory blocks based on the amount of free memory blocks.

3. The system of claim 1 , wherein the operations further comprise:

determining that the first set of memory cells are erased based on a state of a first subset of memory cells of the first set of memory cells,

wherein the programming operation is performed responsive further to determining that the first set of memory cells of the first memory block are erased.

4. The system of claim 3 , wherein the operations further comprise:

determining whether the first subset of memory cells are in an erased state; and

erasing the first set of memory cells responsive to determining that the first subset of memory cells are not in the erased state.

5. The system of claim 1 , wherein the operations further comprise:

terminating the erase protocol of the memory device responsive to determining that the value of the metric is above the predetermined threshold.

6. The system of claim 1 , wherein determining that the value of the metric is below the predetermined threshold corresponds to an initial set-up procedure of the memory array.

7. The system of claim 1 , wherein the operations further comprise:

determining that the programming command is with respect to programming single-level cell (SLC) data, and wherein the first set of memory cells of the first memory block are erased to an SLC erase state.

8. A non-transitory computer-readable storage medium storing executable instructions that, when executed by a controller managing a memory device, cause the controller to:

determine a value of a metric associated with a program-erase cycle (PEC) of one or more memory blocks of a memory array of the memory device, wherein the memory array comprises a plurality of memory blocks, wherein each memory block of the plurality of memory blocks comprises a set of memory cells of a plurality of memory cells, and wherein a first memory block comprises a first set of memory cells;

initiate an erase protocol of a memory device responsive to determining that the value of the metric is below a predetermined threshold;

erase less than a predetermined portion of free sets of memory cells associated with one or more free memory blocks of the plurality of memory blocks;

subsequent to erasing less than the predetermined portion of free sets of memory cells, receive a programming command directed to the first set of memory cells; and

perform a programming operation with respect to the first set of memory cells responsive to receiving the programming command.

9. The non-transitory computer-readable storage medium of claim 8 , wherein the controller is further to:

determine, responsive to initiating the erase protocol, an amount of free memory blocks comprising sets of free memory cells of the plurality of memory cells; and

erasing memory cells of a portion of the free memory blocks based on the amount of free memory blocks.

10. The non-transitory computer-readable storage medium of claim 8 , wherein the controller is further to:

determine that the first set of memory cells are erased based on a state of a first subset of memory cells of the first set of memory cells,

wherein the programming operation is performed responsive further to determining that the set first of memory cells of the first memory block are erased.

11. The non-transitory computer-readable storage medium of claim 10 , wherein the controller is further to:

determine whether the first subset of memory cells are in an erased state; and

erase the first set of memory cells responsive to determining that the first subset of memory cells are not in the erased state.

12. The non-transitory computer-readable storage medium of claim 8 , wherein the controller is further to:

terminate the erase protocol of the memory device responsive to determining that the value of the metric is above the predetermined threshold.

13. The non-transitory computer-readable storage medium of claim 8 , wherein the metric comprises an average program-erase cycle count of the plurality of memory blocks of the memory array.

14. The non-transitory computer-readable storage medium of claim 8 , wherein the controller is further to:

determine that the programming command is with respect to programming single-level cell (SLC) data, and wherein the first set of memory cells of the first memory block are erased to an SLC erase state.

15. A method comprising:

determining a value of a metric associated with a program-erase cycle (PEC) of one or more memory blocks of a memory device, wherein the memory device comprises a plurality of memory blocks, wherein each memory block of the plurality of memory blocks comprises a set of memory cells of a plurality of memory cells, and wherein a first memory block comprises a first set of memory cells;

responsive to determining that the value of the metric is below a predetermined threshold, initiating an erase protocol of the memory device;

erasing less than a predetermined portion of free sets of memory cells associated with one or more free memory blocks of the plurality of memory blocks;

subsequent to erasing less than the predetermined portion of free sets of memory cells, receiving a programming command directed to the first set of memory cells; and

performing a programming operation with respect to the first set of memory cells responsive to receiving the programming command.

16. The method of claim 15 , further comprising:

determining, responsive to initiating the erase protocol, an amount of free memory blocks comprising sets of free memory cells of the plurality of memory cells; and

erasing memory cells of a portion of the free memory blocks based on the amount of free memory blocks.

17. The method of claim 15 , further comprising:

determining that the first set of memory cells are erased based on a state of a first subset of memory cells of the first set of memory cells,

wherein the programming operation is performed responsive further to determining that the first set of memory cells of the first memory block are erased.

18. The method of claim 15 , further comprising:

terminating the erase protocol of the memory device responsive to determining that the value of the metric is above the predetermined threshold.

19. The method of claim 15 , wherein the metric comprises an average program-erase cycle count of the plurality of memory blocks of the memory device.

20. The method of claim 15 , further comprising:

determining that the programming command is with respect to programming single-level cell (SLC) data, and wherein the first set of memory cells of the first memory block are erased to an SLC erase state.