Flash backed DRAM module with a selectable number of flash chips
View Patent ↗A memory device for use with a primary power source and a backup power source, includes: volatile memory; an interface for connecting to a backup power source; a plurality of ports, each of which is for receiving a different corresponding non-volatile memory chip; a plurality of interfaces, each of which is for communicating through a different corresponding one of the plurality of ports with any non-volatile memory connected to that port; a controller that is programmed to activate a selectable set of the plurality of interfaces depending on which ports are to receive non-volatile memory chips, wherein said controller is also programmed to react to a loss of power from the primary power source by moving data from the volatile memory through the selected interfaces to whatever non-volatile memory is connected to the selectable set of interfaces.
1. A memory device for use with a primary power source and a backup power source, the memory device comprising:
volatile memory;
a first interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source;
a plurality of ports, each of which is for receiving a different corresponding non-volatile memory chip;
a plurality of memory chip interfaces, each of which is for communicating through a different corresponding one of the plurality of ports with any non-volatile memory chip connected to that port;
a controller that is programmed to activate a selectable set of the plurality of memory chip interfaces depending on which ports are to receive non-volatile memory chips, wherein said controller is also programmed to react to a loss of power from the primary power source by moving data from the volatile memory through the activated set of memory chip interfaces to whatever non-volatile memory chip is connected to the selectable set of the plurality of memory chip interfaces.
2. The memory device of claim 1 , wherein the volatile memory size is one gigabyte and the controller is programmed to activate four ports.
3. The memory device of claim 1 , wherein the plurality of memory chip interfaces comprises four memory chip interfaces, wherein non-volatile memory chips are connected to two of the four memory chip interfaces, and wherein the controller is programmed to activate the two memory chip interfaces to which non-volatile memory chips are connected.
4. The memory device of claim 1 , wherein the non-volatile memory comprises electrically erasable programmable read-only memories (EEPROMs).
5. The memory device of claim 1 , wherein the controller comprises at least one of an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA).
6. The memory device of claim 1 , wherein power from the backup power source is primarily from a capacitor.
7. The memory device of claim 1 , wherein power from the backup power source is primarily from a super capacitor.
8. The memory device of claim 1 , wherein the controller is further programmed to move data from whatever non-volatile memory is connected to the selectable set of memory chip interfaces to the volatile memory upon a restoration of power of the primary power source.
9. The memory device of claim 1 , wherein each of the plurality of ports comprise holes, pads, or lands of a printed circuit board.
10. The memory device of claim 1 , wherein the controller further comprises a configuration memory for storing port-data identifying which of the plurality of ports is connected to a non-volatile memory device and the memory device further comprising a configuration data bus for reading and writing the port-data.
11. A method of operating a system including volatile memory, a plurality of ports, each of which is for receiving a different corresponding non-volatile memory chip, and a plurality of memory chip interfaces, said method comprising:
activating a selectable set of the plurality of memory chip interfaces depending on which ports are to receive a selectable number of non-volatile memory chips;
detecting a power failure of a primary power source for the volatile memory; and
in response to detecting the power failure: powering the volatile memory with a backup power source and moving data stored in the volatile memory to whatever non-volatile memory chip is connected to the selectable set of the plurality of memory chip interfaces.
12. The method of claim 11 , wherein the volatile memory size is one gigabyte and the selectable number is four.
13. The method of claim 11 , wherein the non-volatile memory comprises electrically erasable programmable read-only memories (EEPROMs).
14. The method of claim 11 , further comprising moving data from the non-volatile memory to the volatile memory upon a restoration of power of the primary power source.
15. The method of claim 11 , wherein power from the backup power source is primarily from a capacitor.
16. The method of claim 11 , wherein power from the backup power source is primarily from a super capacitor.