IP Library Granted Patent US 11,301,318
Granted Patent B2
US 11,301,318 · App. 17/227,231 · Granted Apr 12, 2022

Method and system for managing memory device

Inventors: Sanghoon Chu (San Jose, CA); Scott Jinn (Diamond Bar, CA); Yuriy Pavlenko (Mission Viejo, CA); Kum-Jung Song (Santa Clara, CA)
Assignee: Western Digital Technologies, Inc.
G06F11/0793G06F11/076G06F11/0727G11C29/00G11C29/44G11C29/52G06F2201/81G06F2201/85G06F2201/88
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Quick Facts
Patent No.
US 11,301,318
App. No.
17/227,231
Granted
Apr 12, 2022
Kind
B2
Abstract

The subject technology provides for managing a data storage system. A data operation error for a data operation initiated in a first non-volatile memory die of a plurality of non-volatile memory die in the data storage system is detected. An error count for an error type of the data operation error for the first non-volatile memory die is incremented. The incremented error count satisfies a first threshold value for the error type of the data operation error is determined. The first non-volatile memory die is marked for exclusion from subsequent data operations.

Claims (58)

1. A method for managing a data storage system, the method comprising:

detecting a first memory operation error of a first memory device of memory devices in the data storage system;

detecting a second memory operation error of the first memory device;

incrementing a first error type consecutive count when the first and second memory operation errors are of a first error type and detected consecutively;

incrementing a device consecutive error count, and refraining from incrementing the first error type consecutive count, when the first and second memory operation errors are of different error types and detected consecutively; and

identifying the first memory device to be excluded from participating in subsequent memory operations when the first error type consecutive count satisfies a first threshold value for the first error type.

2. The method of claim 1 , wherein:

when the first and second memory operation errors are of the first error type and detected consecutively, the device consecutive error count is maintained without being incremented; and

when the first and second memory operation errors are detected without being consecutive to each other, the first error type consecutive count and the device consecutive error count are maintained without being incremented.

3. The method of claim 1 , wherein:

when the first error type consecutive count satisfies the first threshold value for the first error type, identifying the first memory device comprises identifying the first memory device to be excluded from participating in subsequent memory operations of a first memory operation type, while permitting the first memory device to participate in subsequent memory operations of a second memory operation type; and

wherein the first memory operation type is different from the second memory operation type.

4. The method of claim 3 , wherein the first memory operation type is a write operation type, and the second memory operation type is a read operation type.

5. The method of claim 1 , comprising: identifying the first memory device to be excluded from participating in subsequent memory operations when the device consecutive error count satisfies a second threshold value.

6. The method of claim 1 , wherein:

the first error type is associated with a first memory operation type; and

the method comprises: resetting the first error type consecutive count associated with the first error type for the first memory device when a memory operation of the first memory operation type is successfully completed for the first memory device.

7. The method of claim 1 , wherein:

the different error types are associated with first and second memory operation types; and

the method comprises: resetting the device consecutive error count for the first memory device when a memory operation of a third operation type is successfully completed for the first memory device.

8. The method of claim 1 , wherein when the first and second memory operation errors of the first memory device are detected without being consecutive to each other, the first error type consecutive count and the device consecutive error count are maintained without being incremented.

9. A data storage system, comprising:

memory devices; and

one or more controllers configured to cause:

detecting a first memory operation error of a first memory device of the memory devices;

detecting a second memory operation error of the first memory device;

incrementing a first error type consecutive count when the first and second memory operation errors are of a first error type and detected consecutively;

incrementing a device consecutive error count, and refraining from incrementing the first error type consecutive count, when the first and second memory operation errors are of different error types and detected consecutively; and

identifying the first memory device to be excluded from participating in subsequent memory operations when the first error type consecutive count satisfies a first threshold value for the first error type.

10. The data storage system of claim 9 , wherein:

when the first and second memory operation errors are of the first error type and detected consecutively, the one or more controllers are configured to cause the device consecutive error count to be maintained without being incremented; and

when the first and second memory operation errors are detected without being consecutive to each other, the one or more controllers are configured to cause the first error type consecutive count and the device consecutive error count to be maintained without being incremented.

11. The data storage system of claim 9 , wherein:

when the first error type consecutive count satisfies the first threshold value for the first error type, identifying the first memory device comprises identifying the first memory device to be excluded from participating in subsequent memory operations of a first memory operation type while permitting the first memory device to participate in subsequent memory operations of a second memory operation type; and

wherein the first memory operation type is different from the second memory operation type.

12. The data storage system of claim 11 , wherein the first memory operation type is a write operation type, and the second memory operation type is a read operation type.

13. The data storage system of claim 9 , wherein the one or more controllers are configured to cause identifying the first memory device to be excluded from participating in subsequent memory operations when the device consecutive error count satisfies a second threshold value.

14. The data storage system of claim 13 , wherein the second threshold value is greater than the first threshold value.

15. The data storage system of claim 9 , wherein:

the first error type is associated with a first memory operation type; and

the one or more controllers are configured to cause: resetting the first error type consecutive count associated with the first error type for the first memory device when a memory operation of the first memory operation type is successfully completed for the first memory device.

16. The data storage system of claim 9 , wherein:

the different error types are associated with first and second memory operation types; and

the one or more controllers are configured to cause: resetting the device consecutive error count for the first memory device when a memory operation of a third operation type is successfully completed for the first memory device.

17. The data storage system of claim 9 , wherein the first error type consecutive count comprises a cumulative error count for all blocks of the first memory device.

18. The data storage system of claim 9 , wherein:

the first error type comprises one of a program error type, a read error type, or an erase error type;

the one or more controllers are configured to cause maintaining a respective error type consecutive count for the first memory device for each of the program error type, the read error type, and the erase error type; and

the one or more controllers are configured to cause maintaining a respective threshold value for each of the program error type, the read error type, and the erase error type.

19. An apparatus, comprising:

means for detecting a first memory operation error of a first memory device of memory devices in a data storage system;

means for detecting a second memory operation error of the first memory device;

means for incrementing a first error type consecutive count when the first and second memory operation errors are of a first error type and detected consecutively;

means for incrementing a device consecutive error count, and refraining from incrementing the first error type consecutive count, when the first and second memory operation errors are of different error types and detected consecutively; and

means for identifying the first memory device to be excluded from participating in subsequent memory operations when the first error type consecutive count satisfies a first threshold value for the first error type.

20. The apparatus of claim 19 , wherein:

when the first error type consecutive count satisfies the first threshold value for the first error type, the means for identifying the first memory device comprises means for identifying the first memory device to be excluded from participating in subsequent memory operations of a first memory operation type, while permitting the first memory device to participate in subsequent memory operations of a second memory operation type; and

wherein the first memory operation type is different from the second memory operation type.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2021
From: JINN, SCOTT; PAVLENKO, YURIY; SONG, KUM-JUNG; CHU, SANGHOON
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055948/0861 →