System and method for destructive purge of memory device
View Patent ↗A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by the power supply and activates the switching circuit to apply the voltage and current to the memory circuits. The controller determines whether the memory circuits have been destroyed by monitoring current flow into the memory circuits.
1. A system for destructively purging a memory device, the system comprising:
a converter configured to supply a first voltage and current;
a switching circuit electrically coupled to the converter and a first memory device, the switching circuit comprising a switch configured to electrically connect the converter to a memory circuit of the first memory device; and
a first controller configured to activate the switch to apply the first voltage and current of the converter to the memory circuit of the first memory device to cause latch-up to occur in a transistor in the memory circuit of the first memory device.
2. The system of claim 1 , wherein the first controller is further configured to activate the switch until the transistor in the memory circuit of the first memory device is destroyed.
3. The system of claim 1 , wherein the first controller is further configured to activate the switch in response to a condition occurring in the system.
4. The system of claim 1 , wherein the first controller is further configured to activate the switch in response to a condition occurring externally of the system.
5. The system of claim 1 , wherein the first controller is further configured to receive a command and to activate the switch in response to receiving the command.
6. The system of claim 1 , further comprising a second controller coupled to the first memory device and configured to access data in the first memory device.
7. The system of claim 6 , wherein the system further comprises a plurality of memory devices coupled to the second controller and the switching circuit, the second controller configured to access data in the plurality of memory devices, the switching circuit further comprising a plurality of switches corresponding to the plurality of memory devices, the first controller further configured to select each memory device from the plurality of memory devices individually, activate the switch corresponding to the selected memory device to apply the first voltage and current to a memory circuit of the selected memory device to destroy a transistor in the memory circuit of the selected memory device, and deactivate the switch corresponding to the selected memory device before selecting a next memory device in the plurality of memory devices.
8. The system of claim 1 , wherein the converter is further configured to convert an input voltage and current from a power source into the first voltage and current.
9. The system of claim 1 , wherein the converter comprises a current detector configured to detect a current flow in the memory circuit of the first memory device, the first controller further configured to deactivate the switch if the current flow is below a threshold value indicating that the transistor in the memory circuit of the memory device is destroyed.
10. The system of claim 9 , wherein the first controller is further configured to deactivate the switch if the current flow is not below the threshold value at a predetermined time after the switch is activated, select a second voltage and current comprising a higher voltage or current than the first voltage and current, and reactivate the switch to apply the second voltage and current to the memory circuit of the first memory device to destroy the transistor in the memory circuit of the first memory device.
11. A method for destructively purging a memory device, the method comprising:
supplying a first voltage and current; and
applying the first voltage and current to a memory circuit of a first memory device to cause latch-up to occur in a transistor in the memory circuit of the first memory device.
12. The method of claim 11 , wherein applying the first voltage and current to the memory circuit of the first memory device continues until the transistor in the memory circuit of the first memory device is destroyed.
13. The method of claim 11 , wherein applying the first voltage and current to the memory circuit of the first memory device occurs in response to a condition.
14. The method of claim 11 , further comprising receiving a command, wherein applying the first voltage and current to the memory circuit of the first memory device occurs in response to receiving the command.
15. The method of claim 11 , further comprising selecting the first memory device from a plurality of memory devices.
16. The method of claim 11 , further comprising:
detecting a current flow through the memory circuit of the first memory device;
determining the current flow is above a threshold value indicating the transistor in the memory circuit of the first memory device is not destroyed;
selecting a second voltage and current comprising a higher voltage or current than the first voltage and current; and
applying the second voltage and current to the memory circuit of the first memory device to destroy the transistor in the memory circuit of the first memory device.
17. The method of claim 11 , further comprising applying the first voltage and current to a memory circuit of a second memory device to destroy a transistor in the memory circuit of the second memory device.
18. A system for destructively purging a memory device, the system comprising:
means for supplying a first voltage and current; and
means for applying the first voltage and current to a memory circuit of a memory device to cause latch-up to occur in a transistor in the memory circuit.
19. The system of claim 18 , further comprising means for determining whether the transistor is destroyed.
20. The system of claim 19 , further comprising means for applying a second voltage and current to the memory circuit to destroy the transistor, the second voltage and current comprising a higher voltage or current than the first voltage and current.