IP Library Granted Patent US 12,382,588
Granted Patent B2
US 12,382,588 · App. 18/360,094 · Granted Aug 5, 2025

Printed circuit board having a temperature profiling connection pad

Inventors: Uthayarajan A/L Rasalingam (Penang, MY); Choo Par Tan (Penang, MY); Mathavan Valu (Pulau Pinang, MY)
Assignee: Sandisk Technologies, Inc.
H05K3/3436B23K1/0016H05K1/0268H05K1/111B23K2101/42H05K1/0266H05K2203/163
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Quick Facts
Patent No.
US 12,382,588
App. No.
18/360,094
Granted
Aug 5, 2025
Kind
B2
Abstract

A printed circuit board (PCB) includes an identified temperature profiling location. The identified temperature profiling location may be a connection pad from a grid of connection pads on the PCB. The connection pad may be located near a center of the grid of connection pads. The connection pad may be coupled to a no-connect pin of an electronic component that is surface mounted to the PCB. Traces extend from the connection pad to test pads provided near a perimeter of the grid of connection pads. A temperature measurement device may be coupled to the test pads, which enables the temperature measurement device to capture accurate temperature readings underneath the electronic component during a reflow profiling process.

Claims (32)

1. A printed circuit board (PCB), comprising:

a grid of connection pads, each connection pad of the grid of connection pads receiving a corresponding connection point from a grid of connection points associated with an electronic component when the electronic component is surface mounted to the PCB;

a test pad positioned proximate to a perimeter of the grid of connection pads, the test pad acting as an attachment point for a temperature measurement device that measures a temperature proximate to an identified connection pad of the grid of connection pads; and

a trace extending from the identified connection pad of the grid of connection pads to the test pad.

2. The PCB of claim 1 , wherein the identified connection pad is located proximate to a center of the grid of connection pads.

3. The PCB of claim 1 , wherein the identified connection pad is associated with a no-connect connection point from the grid of connection points.

4. The PCB of claim 1 , wherein the trace extends from the identified connection pad in a dual trace configuration.

5. The PCB of claim 1 , wherein the trace extends from the identified connection pad using a double dog bone configuration.

6. The PCB of claim 1 , wherein a wire of the temperature measurement device is soldered to the test pad.

7. The PCB of claim 6 , wherein the wire of the temperature measurement device and the test pad are at least partially covered with an insulation material.

8. The PCB of claim 1 , wherein the trace and a wire of the temperature measurement device are formed from copper.

9. A printed circuit board (PCB), comprising:

a grid of connection means adapted to receive interconnection means associated with an integrated circuit;

a testing means positioned proximate to a perimeter of the grid of connection means, the testing means adapted to receive wires of a temperature measurement means that measures a temperature proximate to an identified connection means of the grid of connection means; and

a conducting means extending from the identified connection means of the grid of connection means to the testing means.

10. The PCB of claim 9 , wherein the identified connection means is adapted to receive a particular interconnection means associated with the integrated circuit.

11. The PCB of claim 10 , wherein the particular interconnection means is selected from a group comprising:

a no-connect interconnection means;

a do not connect interconnection means; and

a do not use interconnection means.

12. The PCB of claim 10 , wherein the conducting means and the wires of the temperature measurement means are formed from copper.

13. The PCB of claim 9 , wherein the identified connection means is located proximate to a center of the grid of connection means.

14. A printed circuit board (PCB), comprising:

a grid of connection pads adapted to receive connection points of a grid of connection points associated with an electronic component surface mounted to the PCB;

a test pad operable to be coupled to at least a portion of a temperature measurement device that measures a temperature proximate to an identified connection pad of the grid of connection pads, the test pad located proximate to a perimeter of the grid of connection pads; and

a trace extending between the identified connection pad and the test pad.

15. The PCB of claim 14 , wherein the identified connection pad is in a center portion of the grid of connection pads.

16. The PCB of claim 14 , wherein the identified connection pad is associated with a no-connect connection point of the grid of connection points.

17. The PCB of claim 14 , wherein the trace has a dual trace configuration.

18. The PCB of claim 14 , wherein the trace has a double dog bone configuration.

19. The PCB of claim 14 , wherein a wire of the temperature measurement device is soldered to the test pad.

20. The PCB of claim 19 , wherein the wire of the temperature measurement device and the test pad are at least partially covered with an insulation material.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2023
From: RASALINGAM, UTHAYARAJAN A/L; TAN, CHOO PAR; VALU, MATHAVAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 064406/0593 →
Continuity (2)
Provisional Application 63507507 · Jun 12, 2023
Related Publication 20240414851A1 · Dec 12, 2024
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