Die stitching and harvesting of arrayed structures
Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.
1. A multi-die structure comprising:
a first front-end-of-the line (FEOL) die area of a first die patterned into a semiconductor substrate and a second FEOL die area of a second die patterned into the semiconductor substrate, the second FEOL die area separate from the first FEOL die area;
wherein the first FEOL die area includes a first input/output region, and the second FEOL die area includes a second input/output region;
a back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area and the second FEOL die area, the BEOL build-up structure comprising:
a first partial metallic seal adjacent to the first input/output region;
a second partial metallic seal adjacent to the second input/output region;
a die-to-die routing connecting the first input/output region and the second input/output region and extending through first openings in the first partial metallic seal and second openings in the second partial metallic seal; and
a metallic seal ring completely around the first FEOL die area, the second FEOL die area, and the die-to-die routing.
2. The multi-die structure of claim 1 , wherein the first die and the second die are both network dies.
3. The multi-die structure of claim 1 , wherein the first die and the second die are each selected from the group consisting of a graphics processing unit (GPU), a central processing unit (CPU), a neural engine, an artificial intelligence (AI) engine, and a signal processor.
4. The multi-die structure of claim 1 , wherein the BEOL build-up structure further comprises a plurality of service structures between the first input/output region and the second input/output region.
5. A multi-die structure comprising:
a routing substrate;
a logic chip mounted on the routing substrate;
a chip mounted on the routing substrate adjacent to the logic chip, wherein the chip comprises:
a first front-end-of-the line (FEOL) die area of a first die patterned into a semiconductor substrate and a second FEOL die area of a second die patterned into the semiconductor substrate, the second FEOL die area separate from the first FEOL die area;
wherein the first FEOL die area includes a first input/output region and a third input/output region, and the second FEOL die area includes a second input/output region;
a back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area and the second FEOL die area, the BEOL build-up structure comprising:
a first partial metallic seal adjacent to the first input/output region;
a second partial metallic seal adjacent to the second input/output region; and
a die-to-die routing connecting the first input/output region and the second input/output region and extending through first openings in the first partial metallic seal and second openings in the second partial metallic seal;
wherein the third input/output region is located adjacent to the logic chip and is electrically connected with the logic chip with routing substrate wiring.
6. The multi-die structure of claim 5 , wherein the first die and the second die are each independently selected from the group consisting of static random-access memory, magnetic random-access memory, nonvolatile random-access memory, dynamic random-access memory, NAND, and cache memory.
7. The multi-die structure of claim 5 , wherein the first die is a memory cache die, and the second die is a memory die.
8. The multi-die structure of claim 5 , wherein the first die includes a data buffer not included in the second die.
9. The multi-die structure of claim 5 , wherein the first die is a controller memory die configured to communicate with the logic chip and the second die is a service memory die configured to communicate with the logic chip through the controller memory die.
10. A multi-die structure comprising:
a first front-end-of-the line (FEOL) die area of a first die patterned into a semiconductor substrate and a second FEOL die area of a second die patterned into the semiconductor substrate, the second FEOL die area separate from the first FEOL die area;
wherein the first FEOL die area includes a first input/output region, and the second FEOL die area includes a second input/output region;
a back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area and the second FEOL die area, the BEOL build-up structure comprising:
a first partial metallic seal adjacent to the first input/output region;
a second partial metallic seal adjacent to the second input/output region; and
a die-to-die routing connecting the first input/output region and the second input/output region and extending through first openings in the first partial metallic seal and second openings in the second partial metallic seal;
wherein the semiconductor substrate, the first FEOL die area, second FEOL die area, and BEOL build-up structure form a first die level; and
a second die level hybrid bonded to the first die level, the second die level including a third front-end-of-the line (FEOL) die area of a third die patterned into a second semiconductor substrate and a fourth FEOL die area of a fourth die patterned into the second semiconductor substrate, the fourth FEOL die area separate from the third FEOL die area.
11. The multi-die structure of claim 10 , wherein the semiconductor substrate of the first die level is bonded to a second BEOL build-up structure of the second die level spanning over the third FEOL die area and the fourth FEOL die area.
12. The multi-die structure of claim 11 , further comprising a plurality of through silicon vias extending through the semiconductor substrate.
13. The multi-die structure of claim 11 , wherein the second BEOL build-up structure of the second die comprises a second die-to-die routing connecting the third FEOL die area and the fourth FEOL die area.
14. The multi-die structure of claim 13 , wherein the second die-to-die routing extends through a third partial metallic seal adjacent the third FEOL die area, and a fourth partial metallic seal adjacent the fourth FEOL die area.