Interconnecting a plurality of dies having spare input/output circuit
Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.
1. A die structure comprising:
a semiconductor substrate;
a first front-end-of-the-line (FEOL) die area of a first die patterned into the semiconductor substrate, the first FEOL die area including a plurality of input/output (I/O) circuits; and
a back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area, the BEOL build-up structure including a plurality of die I/O connections coupled to the plurality of I/O circuits with a plurality of routings, wherein an I/O circuit of the plurality of I/O circuits is not coupled to a die I/O connection.
2. The die structure of claim 1 , wherein each die I/O connection is selected from the group consisting of a pad and a pin.
3. The die structure of claim 1 , comprising a first group of the plurality of routings with a first characteristic routing pattern, and a second group of the plurality of routings with a second characteristic routing pattern, wherein a difference in the first characteristic routing pattern and the second characteristic routing pattern is correlated with the I/O circuit not being coupled to a die I/O connection.
4. The die structure of claim 1 , wherein each input/output circuit of the plurality of input/output circuits includes a digital I/O component and an analog I/O component.
5. The die structure of claim 1 , wherein the I/O circuit of the plurality of I/O circuits that is not coupled to a die I/O connection is a spare I/O circuit or a bad I/O circuit.
6. The die structure of claim 1 , wherein the plurality of I/O circuits is arranged in series.
7. The die structure of claim 6 , wherein the I/O circuit that is not coupled to a die I/O connection is at an end of the series.
8. The die structure of claim 6 , wherein the I/O circuit that is not coupled to a die I/O connection is within the series.
9. The die structure of claim 1 further comprising:
a second FEOL die area of a second die patterned into the semiconductor substrate
wherein the BEOL build-up structure spans over the second die area, the BEOL build-up structure comprising a die-to-die routing electrically connecting the first die to the second die.
10. The die structure of claim 9 , further comprising a metallic seal around the first die area, the second die area and the die-to die routing.
11. The die structure of claim 9 , further comprising one or more barrier layers including a substantially uniform thickness spanning along die edges of the die structure substantially orthogonal to metal layers of the BEOL build-up structure.
12. The die structure of claim 11 , wherein the one or more barrier layers includes an oxide layer.
13. The die structure of claim 11 , wherein the one or more barrier layers includes a nitride layer.
14. The die structure of claim 9 , wherein the first die and the second die are each selected from the group consisting of a graphics processing unit (GPU) and a central processing unit (CPU).
15. The die structure of claim 9 , wherein the die-to-die routing includes a first die routing within the first die area, a second die routing within the second die area, and a stitch routing physically connecting the first die routing to the second die routing.
16. The die structure of claim 15 , wherein the stitch routing has a wider line width than the first die routing and the second die routing, and the stitch routing has a coarser line pitch than the first die routing and the second die routing.