Intelligent chip placement within a three-dimensional chip stack
An integrated circuit (IC) stack device for thermal management is disclosed. The IC stack device can include a primary IC having a first set of cores with a ratio of first enabled cores and first disabled cores. The IC stack device can also have a supplementary IC interfaced with the primary IC, and having a second set of cores with a second ratio of second enabled cores and second disabled cores, with the second ratio being less than the first ratio. The integrated circuit stack device can also include a cooling element located such that the primary integrated circuit is between the cooling element and the supplementary integrated circuit. The cooling element can be designed to facilitate heat dissipation of the first and second enabled cores of the primary integrated circuit and the supplementary integrated circuit.
1. An integrated circuit (IC) stack device comprising:
a primary IC having
a first set of cores with a first ratio of first enabled cores and first disabled cores wherein the first disabled cores include at least one functional disabled core and at least one non-functional disabled core,
a first side on which the first set of cores is located, and
a second side opposing the first side;
a supplementary IC interfaced with the primary IC and having
a second set of cores with a second ratio of second enabled cores and second disabled cores, the second ratio less than the first ratio, wherein the second enabled cores include at least one functional enabled core corresponding to the at least one non-functional disabled core on the primary IC and at least one functional spare core corresponding to the at least one functional disabled core on the primary IC, the at least one functional spare core selected to balance thermal distribution of enabled cores within the IC stack,
a third side on which the second set of cores is located, and
a fourth side opposing the third side;
a power source located such that the supplementary IC is between the primary IC and the power source, wherein the supplementary IC includes one or more through-silicon vias (TSVs) configured to enable power delivery from the power source to the primary IC; and
a cooling element located such that the primary IC is between the cooling element and the supplementary IC, the primary IC having a higher number of functional cores than the supplementary IC and the cooling element adapted to facilitate heat dissipation of the first and second enabled cores of the primary IC and the supplementary IC.
2. The device according to claim 1 , wherein the first set of cores and the second set of cores include one or more microprocessors.
3. The device according to claim 1 , wherein the first side of the primary IC is interfaced with the third side of the supplementary IC.
4. The device according to claim 1 , wherein the first side of the primary IC is interfaced with the fourth side of the supplementary IC.
5. The device according to claim 1 , wherein the second side of the primary IC is interfaced with the third side of the supplementary IC.
6. The device according to claim 1 , wherein the primary IC and the secondary IC each include at least one data bus configured to facilitate communication between cores on a respective IC.
7. The device according to claim 6 , further including
a primary databus on the primary IC; and
a logic switching element connected to a particular enabled core of the second enabled cores and
a particular disabled core of the first disabled cores, the logic switching element configured to route signals from the particular enabled core to the primary data bus.
8. An integrated circuit (IC) stack device comprising:
a supplementary IC having
a first side,
a first set of cores with first enabled cores and first disabled cores, the first set of cores on the first side,
a second side opposing the first side, and
a first data bus;
a primary IC interfaced with the supplementary IC and having
a second set of cores with second enabled cores and second disabled cores,
wherein the second disabled cores include at least one functional disabled core and at least one non-functional disabled core,
wherein the first enabled cores include at least one functional enabled core corresponding to the at least one non-functional disabled core on the primary IC and at least one functional spare core corresponding to the at least one functional disabled core on the primary IC, the at least one functional spare core selected to balance thermal distribution of enabled cores within the IC stack,
a third side on which the second set of cores is located,
a fourth side opposing the third side, and
a second data bus configured to facilitate communication between the first set of cores and the second set of cores;
a power source configured to deliver power to the primary IC via one or more through-silicon vias (TSVs) in the supplementary IC, wherein the supplementary IC is located between the primary IC and the power source; and
a cooling element located such that the primary IC is between the cooling element and the supplementary IC, the primary IC having a higher number of functional cores than the supplementary IC and the cooling element adapted to facilitate heat dissipation of the first and second enabled cores of the supplementary IC and the primary IC.
9. The device according to claim 8 , wherein the first set of cores and the second set of cores include one or more microprocessors.
10. The device according to claim 8 , wherein the first side of the supplementary IC is interfaced with the third side of the primary IC.
11. The device according to claim 8 , wherein the first side of the supplementary IC is interfaced with the fourth side of the primary IC.
12. The device according to claim 8 , wherein the second side of the supplementary IC is interfaced with the third side of the primary IC.
13. The device according to claim 8 , wherein the first data bus is capable of facilitating communication between respective cores of the first set of cores.
14. The device according to claim 8 , wherein the primary IC includes a logic switching element connected to a particular enabled core of the first enabled cores and a particular disabled core of the second disabled cores, the logic switching element configured to route signals from the particular enabled core to the second data bus.