Systems and methods for forming die sets with die-to-die routing and metallic seals
Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.
1. A multi-die structure including:
a first front-end-of-the line (FEOL) die area of a first die patterned into a semiconductor substrate and a second FEOL die area of a second die patterned into the semiconductor substrate, the second FEOL die area separate from the first FEOL die area;
wherein the first FEOL die area includes a first die-to-die input/output circuit region, and the second FEOL die area includes a second die-to-die input/output circuit region;
a back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area and the second FEOL die area, the BEOL build-up structure comprising a die-to-die routing to electrically connect the first die-to die input/output circuit region to the second die-to-die input/output circuit region.
2. The multi-die structure of claim 1 , wherein the first FEOL die area includes a first core logic circuit region, and the second FEOL die area includes a second core logic circuit region.
3. The multi-die structure of claim 1 , wherein the die-to-die routing includes a first die routing, a second die routing, and a stitch routing physically connecting the first die routing to the second die routing.
4. The multi-die structure of claim 3 , wherein the stitch routing has a wider line width than the first die routing and the second die routing, and the stitch routing has a coarser line pitch than the first die routing and the second die routing.
5. The multi-die structure of claim 1 , wherein the BEOL build-up structure further comprises:
a first metallic seal directly over a first peripheral area of the first FEOL die area;
a second metallic seal directly over a second peripheral area of the second FEOL die area; and
the die-to-die routing extends through a first opening in the first metallic seal and a second opening in the second metallic seal to electrically connect the first die to the second die.
6. The multi-die structure of claim 5 , wherein the die-to-die routing enters the first metallic seal in a lower metal level in the BEOL build-up structure and exits the first metallic seal in an upper metal level in the BEOL build-up structure above the lower metal level.
7. The multi-die structure of claim 5 , wherein the first FEOL die area includes a third die-to-die input/output circuit region including third die routing that terminates near a diced edge of the multi-die structure.
8. The multi-die structure of claim 5 , further comprising one or more barrier layers including a substantially uniform thickness spanning along a diced edge of the multi-die structure substantially orthogonal to metal layers of the BEOL build-up structure.
9. The multi-die structure of claim 1 , further comprising a metallic seal around the first FEOL die area, the second FEOL die area, and the die-to-die routing.
10. The multi-die structure of claim 1 , wherein the first FEOL die area includes a third die-to-die input/output circuit region including third die routing that terminates near a diced edge of the multi-die structure.
11. The multi-die structure of claim 10 , further comprising a plurality of input/output connections coupled to the first die-to-die input/output circuit region and the second die-to-die input/output circuit region.
12. The multi-die structure of claim 10 , wherein the third die-to-die input/output circuit region is not coupled to a die input/output connection.
13. The multi-die structure of claim 1 , wherein the first die-to-die input/output circuit region in includes a driver, and the second die-to-die input/output circuit region includes a receiver.
14. The multi-die structure of claim 13 , wherein the die-to-die routing includes a first die routing and a second die routing, and the second die-to-die input/output circuit region comprises an antenna diode coupled to the second die routing between the receiver and the second die routing.
15. The multi-die structure of claim 14 , wherein the first die-to-die input/output circuit region comprises a second antenna diode coupled to the first die routing between the driver and the first die routing.
16. The multi-die structure of claim 14 , further comprising a detection circuit coupled to the receiver and a second die routing to detect presence of the first die.
17. The multi-die structure of claim 13 , further comprising a buffer enable/disable input to the driver, a first power switch input to the driver, an enable/disable input to the receiver, and a second power switch input to the receiver.
18. The multi-die structure of claim 1 , wherein the first die and the second die are different die types.
19. The multi-die structure of claim 1 , wherein the first die and the second die are a same die type.
20. The multi-die structure of claim 19 , wherein the same die type is selected from the group consisting of a graphics processing unit (GPU) and a central processing unit (CPU).