Interconnecting dies by stitch routing
Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.
1. A die structure comprising:
a semiconductor substrate;
a first front-end-of-the line (FEOL) die area of a first die patterned into the semiconductor substrate, the first FEOL die area including a first input/output circuit region;
a back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area, wherein the BEOL build-up structure further comprises a first metallic seal adjacent to the first input/output circuit region; and
a die edge adjacent to the first input/output circuit region;
wherein the BEOL build-up structure comprises a die-to-die routing connected between the first input/output circuit region and a terminal end of die-to-die routing at the die edge, and the die-to-die routing extends through first openings in the first metallic seal.
2. The die structure of claim 1 , wherein the first input/output circuit region connected to the die-to-die routing is isolated in an off state.
3. The die structure of claim 1 , wherein the die-to-die routing enters the first metallic seal in a lower metal level in the BEOL build-up structure and exits the first metallic seal in an upper metal level in the BEOL build-up structure above the lower metal level.
4. The die structure of claim 1 , further comprising one or more barrier layers including a substantially uniform thickness spanning along the die edge substantially orthogonal to metal layers of the BEOL build-up structure.
5. The die structure of claim 1 :
further comprising a second FEOL die area of a second die patterned into the semiconductor substrate, the second FEOL die area including a second device area and a second input/output circuit region;
wherein the first FEOL die area includes a third input/output circuit region; and
wherein the BEOL build-up structure spans over the second device area, the second input/output circuit region, and the third input/output circuit region, and the BEOL build-up structure comprises a second die-to-die routing connected between the second input/output circuit region and the third input/output circuit region.
6. The die structure of claim 5 , wherein:
the BEOL build-up structure further comprises a second metallic seal adjacent the second input/output circuit region and a third metallic seal adjacent to the third input/output circuit region; and
the second die-to-die routing extends through second openings in the second metallic seal and through third openings in the third metallic seal.
7. A die structure comprising:
a semiconductor substrate;
a first front-end-of-the line (FEOL) die area of a first die patterned into the semiconductor substrate, the first FEOL die area including a first input/output circuit region;
a back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area; and
a die edge adjacent to the first input/output circuit region;
wherein the BEOL build-up structure comprises a die-to-die routing connected between the first input/output circuit region and a terminal end of die-to-die routing at the die edge; and
wherein the first input/output circuit region includes a driver connected to the die-to-die routing.
8. The die structure of claim 7 , further comprising a power switch input and an impedance buffer enable/disable input to the driver.
9. The die structure of claim 7 , further comprising an antenna diode coupled to the die-to-die routing between the driver and the terminal end.
10. A die structure comprising:
a semiconductor substrate;
a first front-end-of-the line (FEOL) die area of a first die patterned into the semiconductor substrate, the first FEOL die area including a first input/output circuit region;
a back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area; and
a die edge adjacent to the first input/output circuit region;
wherein the BEOL build-up structure comprises a die-to-die routing connected between the first input/output circuit region and a terminal end of die-to-die routing at the die edge; and
wherein the first input/output circuit region includes a first receiver connected to the die-to-die routing, a power switch input and an enable/disable input to the first receiver.
11. The die structure of claim 10 , further comprising an antenna diode coupled to the die-to-die routing between the receiver and the terminal end.
12. The die structure of claim 10 , further comprising a power switch input and an enable/disable input to the first receiver.
13. The die structure of claim 12 , wherein the first input/output circuit region includes a second receiver connected to the die-to-die routing.
14. The die structure of claim 13 , wherein the second receiver is a part of a detection circuit, and further comprising a pullup connected to the die-to-die routing between the second receiver and the terminal end.
15. The die structure of claim 14 , further comprising logic connected between an output of the second receiver and the enable/disable input to the first receiver.