Granted Patent B2

US 11,755,211 · App. 17/958,934 · Granted Sep 12, 2023

Inventors: Grishma Shah (San Jose, CA); Daniel Tuers (Kapaa, HI); Sahil Sharma (San Jose, CA); Hua-Ling Cynthia Hsu (Fremont, CA); Yenlung Li (San Jose, CA); Min Peng (San Jose, CA)

Assignee: Western Digital Technologies, Inc.

G06F3/0629G06F3/0614G06F3/0653G06F3/0659G06F3/0679G06F12/0207G06F12/0882

Abstract

Claims (168)

1. A data storage device, comprising:

a NAND memory including:

a plurality of dies that each include a plurality of planes, and

a read/write circuit configured to:

determine initial physical column addresses for each of the plurality of planes in each of the plurality of dies, and

store the initial physical column addresses in the NAND memory; and

a controller coupled to the NAND memory and configured to:

send a first cache read command to the NAND memory, wherein the first cache read command indicating that a three-byte address will follow,

send the three-byte address to the NAND memory, wherein the three-byte address including at least a first die address, a first plane address, and a first page address, and

send a second cache read command to the NAND memory,

wherein the read/write circuit is further configured to:

retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the second cache read command from the controller, wherein the first initial physical column address is associated with the first die address and the first plane address,

retrieve a first page of data stored at the first initial physical column address, wherein the first page of data is associated with the first page address, and

output the first page of data to the controller.

2. The data storage device of claim 1 , wherein the read/write circuit is further configured to determine each of the initial physical column addresses based on a logical column 0.

3. The data storage device of claim 1 , wherein the controller is further configured to send a third cache read command to the NAND memory, wherein the read/write circuit is further configured to:

increment the first page address by one to determine a second page address,

retrieve a second page of data associated with the second page address, and

output the second page of data to the controller.

4. The data storage device of claim 1 , wherein the controller is further configured to:

send a read-transfer command to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the read-transfer command indicating that a one-byte address will follow, and

send the one-byte address to the NAND memory, wherein the one-byte address including a second die address and a second plane address,

wherein the read/write circuit is further configured to:

retrieve a second initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller, wherein the second initial physical column address is associated with the second die address and the second plane address,

retrieve a first set of data stored at the second initial physical column address,

output the first set of data to the controller,

send a data input command to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the data input command indicating that a second one-byte address will follow,

send the second one-byte address to the NAND memory, wherein the second one-byte address including at least a third die address and a third plane address,

send a second set of data to the NAND memory, and

send a program command to the NAND memory,

wherein the read/write circuit is further configured to:

retrieve a third initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the second one-byte address from the controller, wherein the third initial physical column address is associated with the third die address and the third plane address, and

program the second set of data at the third initial physical column address after the NAND memory receives the program command from the controller.

5. The data storage device of claim 1 , wherein the controller is further configured to:

send a read-transfer command to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the read-transfer command indicating that a one-byte address will follow, and

send the one-byte address to the NAND memory, wherein the one-byte address including a second die address and a second plane address,

wherein the read/write circuit is further configured to:

retrieve a second initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller, wherein the second initial physical column address is associated with the second die address and the second plane address,

retrieve a first set of data stored at the second initial physical column address, and

output the first set of data to the controller,

wherein the read/write circuit is further configured to retrieve the second initial physical column address in direct response to the NAND memory receiving the one-byte address from the controller.

6. The data storage device of claim 1 , wherein the controller is further configured to:

send a read-transfer command to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the read-transfer command indicating that a one-byte address will follow, and

send the one-byte address to the NAND memory, wherein the one-byte address including a second die address and a second plane address,

wherein the read/write circuit is further configured to:

retrieve a second initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller, wherein the second initial physical column address is associated with the second die address and the second plane address,

retrieve a first set of data stored at the second initial physical column address, and

output the first set of data to the controller,

wherein the read/write circuit is further configured to determine a plurality of the initial physical column addresses for each of the plurality of planes in each of the plurality of dies, and

wherein the one-byte address further including an initial column identifier, and wherein the second initial physical column address is further associated with the initial column identifier.

7. The data storage device of claim 1 , wherein the controller is further configured to:

send a read-transfer command to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the read-transfer command indicating that a one-byte address will follow, and

send the one-byte address to the NAND memory, wherein the one-byte address including a second die address and a second plane address,

wherein the read/write circuit is further configured to:

retrieve a second initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller, wherein the second initial physical column address is associated with the second die address and the second plane address,

retrieve a first set of data stored at the second initial physical column address, and output the first set of data to the controller,

wherein the read/write circuit is further configured to:

determine one or more bad column addresses for each of the plurality of dies, and

determine the initial physical column addresses based on the one or more bad column addresses.

8. A method, comprising:

sending a first cache read command from a controller to a NAND memory, wherein the first cache read command indicating that a three-byte address will follow;

sending the three-byte address from the controller to the NAND memory, wherein the three-byte address including at least a first die address, a first plane address, and a first page address;

sending a second cache read command from the controller to the NAND memory;

retrieving a first initial physical column address from initial physical column addresses stored in the NAND memory after the NAND memory receives the second cache read command from the controller, wherein the first initial physical column address is associated with the first die address and the first plane address;

retrieving a first page of data stored at the first initial physical column address, wherein the first page of data is associated with the first page address; and

outputting the first page of data from the NAND memory to the controller.

9. The method of claim 8 , further comprising:

determining, with the NAND memory, the initial physical column addresses for each of a plurality of planes in each of a plurality of dies in the NAND memory by determining each of the initial physical column addresses based on a logical column 0;

storing the initial physical column addresses in the NAND memory;

sending a read-transfer command from the controller to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the read-transfer command indicating that a one-byte address will follow;

sending the one-byte address from the controller to the NAND memory, wherein the one-byte address including a second die address and a second plane address;

retrieving a second initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller, wherein the second initial physical column address is associated with the second die address and the second plane address;

retrieving a first set of data stored at the second initial physical column address in the NAND memory; and

outputting the first set of data from the NAND memory to the controller.

10. The method of claim 8 , further comprising:

determining, with the NAND memory, the initial physical column addresses for each of a plurality of planes in each of a plurality of dies in the NAND memory;

storing the initial physical column addresses in the NAND memory;

sending a read-transfer command from the controller to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the read-transfer command indicating that a one-byte address will follow;

sending the one-byte address from the controller to the NAND memory, wherein the one-byte address including a second die address and a second plane address;

retrieving a second initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller, wherein the second initial physical column address is associated with the second die address and the second plane address;

retrieving a first set of data stored at the second initial physical column address in the NAND memory;

outputting the first set of data from the NAND memory to the controller;

sending a data input command from the controller to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the data input command indicating that a second one-byte address will follow;

sending the second one-byte address from the controller to the NAND memory, wherein the second one-byte address including at least a third die address and a third plane address;

retrieving a third initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the second one-byte address from the controller, wherein the third initial physical column address is associated with the third die address and the third plane address;

sending a second set of data from the controller to the NAND memory;

sending a program command from the controller to the NAND memory; and

programming the second set of data at the third initial physical column address in the NAND memory after the NAND memory receives the program command from the controller.

11. The method of claim 8 , further comprising:

sending a third cache read command from the controller to the NAND memory;

incrementing the first page address by one to determine a second page address;

retrieving a second page of data associated with the second page address; and

outputting the second page of data from the NAND memory to the controller.

12. The method of claim 8 , further comprising

determining, with the NAND memory, the initial physical column addresses for each of a plurality of planes in each of a plurality of dies in the NAND memory;

storing the initial physical column addresses in the NAND memory;

sending a read-transfer command from the controller to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the read-transfer command indicating that a one-byte address will follow;

sending the one-byte address from the controller to the NAND memory, wherein the one-byte address including a second die address and a second plane address;

retrieving a second initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller, wherein the second initial physical column address is associated with the second die address and the second plane address, and wherein retrieving the second initial physical column address is in direct response to the NAND memory receiving the one-byte address from the controller;

retrieving a first set of data stored at the second initial physical column address in the NAND memory; and

outputting the first set of data from the NAND memory to the controller.

13. The method of claim 8 , further comprising:

determining, with the NAND memory, a plurality of the initial physical column addresses for each of a plurality of planes in each of a plurality of dies;

storing the initial physical column addresses in the NAND memory;

sending a read-transfer command from the controller to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the read-transfer command indicating that a one-byte address will follow, wherein the one-byte address further includes an initial column identifier;

sending the one-byte address from the controller to the NAND memory, wherein the one-byte address including a second die address and a second plane address;

retrieving a second initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller, wherein the second initial physical column address is associated with the second die address and the second plane address, and wherein the second initial physical column address is further associated with the initial column identifier;

retrieving a first set of data stored at the second initial physical column address in the NAND memory; and

outputting the first set of data from the NAND memory to the controller.

14. The method of claim 8 , further comprising:

determining, with the NAND memory, one or more bad column addresses for each of a plurality of dies;

determining, with the NAND memory, the initial physical column addresses for each of a plurality of planes in each of the plurality of dies in the NAND memory based on the one or more bad column addresses;

storing the initial physical column addresses in the NAND memory;

sending a read-transfer command from the controller to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the read-transfer command indicating that a one-byte address will follow;

sending the one-byte address from the controller to the NAND memory, wherein the one-byte address including a second die address and a second plane address;

retrieving a second initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller, wherein the second initial physical column address is associated with the second die address and the second plane address;

retrieving a first set of data stored at the second initial physical column address in the NAND memory; and

outputting the first set of data from the NAND memory to the controller.

15. An apparatus, comprising:

means for sending a first cache read command from a controller to a NAND memory, wherein the first cache read command indicating that a three-byte address will follow;

means for sending the three-byte address from the controller to the NAND memory, wherein the three-byte address including at least a first die address, a first plane address, and a first page address;

means for sending a second cache read command from the controller to the NAND memory;

means for retrieving a first initial physical column address from initial physical column addresses stored in the NAND memory after the NAND memory receives the second cache read command from the controller, wherein the first initial physical column address is associated with the first die address and the first plane address;

means for retrieving a first page of data stored at the first initial physical column address, wherein the first page of data is associated with the first page address; and

means for outputting the first page of data from the NAND memory to the controller.

16. The apparatus of claim 15 , further comprising:

means for determining, with the NAND memory, the initial physical column addresses for each of a plurality of planes in each of a plurality of dies in the NAND memory by determining each of the initial physical column addresses based on a logical column 0;

means for storing the initial physical column addresses in the NAND memory;

means for sending a read-transfer command from the controller to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the read-transfer command indicating that a one-byte address will follow;

means for sending the one-byte address from the controller to the NAND memory, wherein the one-byte address including a second die address and a second plane address;

means for retrieving a second initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller, wherein the second initial physical column address is associated with the second die address and the second plane address;

means for retrieving a first set of data stored at the second initial physical column address in the NAND memory; and

means for outputting the first set of data from the NAND memory to the controller.

17. The apparatus of claim 15 , further comprising:

means for determining, with the NAND memory, the initial physical column addresses for each of a plurality of planes in each of a plurality of dies in the NAND memory;

means for storing the initial physical column addresses in the NAND memory;

means for sending a read-transfer command from the controller to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the read-transfer command indicating that a one-byte address will follow;

means for sending the one-byte address from the controller to the NAND memory, wherein the one-byte address including a second die address and a second plane address;

means for retrieving a second initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller, wherein the second initial physical column address is associated with the second die address and the second plane address;

means for retrieving a first set of data stored at the second initial physical column address in the NAND memory;

means for outputting the first set of data from the NAND memory to the controller;

means for sending a data input command from the controller to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the data input command indicating that a second one-byte address will follow;

means for sending the second one-byte address from the controller to the NAND memory, wherein the second one-byte address including at least a third die address and a third plane address;

means for retrieving a third initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the second one-byte address from the controller, wherein the third initial physical column address is associated with the third die address and the third plane address;

means for sending a second set of data from the controller to the NAND memory;

means for sending a program command from the controller to the NAND memory; and

means for programming the second set of data at the third initial physical column address in the NAND memory after the NAND memory receives the program command from the controller.

18. The apparatus of claim 15 , further comprising:

means for sending a third cache read command from the controller to the NAND memory;

means for incrementing the first page address by one to determine a second page address;

means for retrieving a second page of data associated with the second page address; and

means for outputting the second page of data from the NAND memory to the controller.

19. The apparatus of claim 15 , further comprising

means for determining, with the NAND memory, the initial physical column addresses for each of a plurality of planes in each of a plurality of dies in the NAND memory;

means for storing the initial physical column addresses in the NAND memory;

means for sending a read-transfer command from the controller to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the read-transfer command indicating that a one-byte address will follow;

means for sending the one-byte address from the controller to the NAND memory, wherein the one-byte address including a second die address and a second plane address;

means for retrieving a second initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller, wherein the second initial physical column address is associated with the second die address and the second plane address, and wherein retrieving the second initial physical column address is in direct response to the NAND memory receiving the one-byte address from the controller;

means for retrieving a first set of data stored at the second initial physical column address in the NAND memory; and

means for outputting the first set of data from the NAND memory to the controller.

20. The apparatus of claim 15 , further comprising:

means for determining, with the NAND memory, a plurality of the initial physical column addresses for each of a plurality of planes in each of a plurality of dies;

means for storing the initial physical column addresses in the NAND memory;

means for sending a read-transfer command from the controller to the NAND memory after the NAND memory stores the initial physical column addresses, wherein the read-transfer command indicating that a one-byte address will follow, wherein the one-byte address further includes an initial column identifier;

means for sending the one-byte address from the controller to the NAND memory, wherein the one-byte address including a second die address and a second plane address;

means for retrieving a second initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller, wherein the second initial physical column address is associated with the second die address and the second plane address, and wherein the second initial physical column address is further associated with the initial column identifier;

means for retrieving a first set of data stored at the second initial physical column address in the NAND memory; and

means for outputting the first set of data from the NAND memory to the controller.

Assignments (8)

Continuity (3)