IP Library Granted Patent US 11,640,243
Granted Patent B2
US 11,640,243 · App. 17/107,597 · Granted May 2, 2023

Supervised learning with closed loop feedback to improve input output consistency of solid state drives

Inventors: Rushang Karia (Tempe, AZ); Mervyn Wongso (Gilbert, AZ); Jacob Schmier (Gilbert, AZ); Kevin Corbin (Chandler, AZ); Lakshmana Rao Chintada (Gilbert, AZ)
Assignee: Western Digital Technologies, Inc.
G06F3/061G06F3/0616G06F3/0679G06F11/34G06F15/76G06N20/00
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Quick Facts
Patent No.
US 11,640,243
App. No.
17/107,597
Granted
May 2, 2023
Kind
B2
Abstract

A method and apparatus is disclosed for using supervised learning with closed loop feedback to improvement of output consistency for memory arrangements, such as a solid state drive.

Claims (51)

1. An arrangement to perform supervised learning with a closed loop feedback for a solid state drive, comprising:

a workload detection engine configured to receive an input command from a host;

a command dispatcher configured to receive the input command from the host;

a memory with a connection for receiving and sending data;

a command processor connected to the command dispatcher, the command processor configured to perform commands provided by the command dispatcher, the command processor connected to the memory through the connection;

an engine configured to receive a set of data from the workload detection engine, the engine configured to calculate throttling latencies for the solid state drive; and

a host responder connected to the command dispatcher and the engine, the host responder configured to respond to the host with completed commands, wherein the workload detection engine is configured to:

calculate a minimum system imposed read and write latency for the solid state drive;

calculate an expected read latency for the solid state drive based on the minimum system imposed read latency;

calculate an expected write latency for the solid state drive based on the minimum system imposed write latency;

calculate an amplification coefficient for write operations and an amplification coefficient for read operations based upon a model;

calculate a final read latency for the solid state drive based upon the calculated expected read latency and the amplification coefficient for read operations; and

calculate a final write latency for the solid state drive based upon the calculated expected write latency and the amplification coefficient for write operations.

2. The arrangement according to claim 1 , wherein the engine is a throttling engine.

3. The arrangement according to claim 1 , wherein the set of data from the workload detection engine is a current workload.

4. The arrangement according to claim 1 , wherein the memory is NAND flash memory.

5. The arrangement according to claim 2 , wherein the throttling engine is connected to the command processor.

6. The arrangement according to claim 5 , wherein the throttling engine provides throttling latencies to the command processor.

7. The arrangement according to claim 1 , wherein the memory is a NOR flash memory.

8. The arrangement according to claim 1 , wherein the memory is a vertical NAND flash memory.

9. The arrangement of claim 1 , wherein a model for the calculating the amplification coefficient for write operations and the amplification coefficient for read operations is a linear regression model.

10. The arrangement of claim 9 , wherein the linear regression model is a second order linear regression model.

11. The arrangement of claim 10 , wherein the second order linear regression model for read operations is of a form of:

ϕ r [ x ]=θ 0 P r 2 +θ 1 P r 2 +θ 2

wherein ϕ r [ x ] is a read amplification factor, P r is a read percentage and θ n values are supervised learning coefficients.

12. The arrangement of claim 11 , wherein the θ n values are calculated from training data.

13. The arrangement of claim 10 , wherein the second order linear regression model for write operations is of a form of:

ϕ w [ x ]=θ 0 P w 2 +θ 1 P w 2 +θ 2

wherein ϕ w [ x ] is a write amplification factor, P W is a write percentage and θ n values are supervised learning coefficients.

14. The arrangement of claim 13 , wherein the θ n values are calculated from training data.

15. The arrangement of claim 1 , wherein the minimum system imposed read latency (L Br ) is calculated as:

L

Br

=

1

R

max

wherein R′ max is a maximum possible input output read operations per second value for the solid state drive.

16. The arrangement of claim 1 , wherein the minimum system imposed write latency (LBW) is calculated as:

L

Bw

=

1

W

max

wherein W′ max is a maximum possible input output read operations per second value for the solid state drive.

17. The arrangement of claim 1 , wherein the calculating the expected read latency and the expected write latency for the solid state drive is based on a workload.

18. The arrangement of claim 1 , wherein the host responder is configured to throttle operations of sending one or more completed commands to the host.

19. The arrangement of claim 18 , wherein the host responder throttles operations based upon not exceeding the final read latency and final write latency.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 055404 FRAME 0942 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0407 →
SECURITY INTEREST Recorded Feb 24, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 055404/0942 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2020
From: KARIA, RUSHANG; WONGSO, MERVYN; SCHMIER, JACOB; CORBIN, KEVIN; CHINTADA, LAKSHMANA RAO
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 054509/0125 →