Controller for quality of service based arbitrations
A method and apparatus for operating a solid state drive is disclosed comprising receiving at least two commands from a host requiring an action by the solid state drive in a preliminary order, ordering the at least two commands based upon a quality of service classification for the at least two commands to a final order and executing the at least two commands on the solid state drive in the final order, wherein an operational parameter of the solid state drive is modified by at least one of the at least two commands.
1. A memory device, comprising:
at least one memory array configured to store data provided to the array; and
a controller coupled to the at least one memory array, wherein the controller is configured to:
receive at least two commands from a host requiring an action by the memory device in a preliminary order;
order the at least two commands based upon a quality of service classification for the at least two commands to a final order, wherein the ordering the at least two commands comprises:
estimating a time of completion for each of the at least two commands;
comparing the estimated time of completion for each of the at least two commands to a threshold; and
reordering the at least two commands; and
execute the at least two commands on the memory device, wherein an operational parameter of the memory device is modified by at least one of the at least two commands.
2. The memory device of claim 1 , wherein the controller is further configured to transmit the at least two commands from the host to the memory device.
3. The memory device of claim 1 , wherein the controller is further configured to transmit a completion notification for each of the at least two commands from the memory device to the host that each of the at least two commands have been completed.
4. The memory device of claim 3 , wherein the controller is further configured to send an interrupt notification to the host from the memory device upon sending the completion notification.
5. The memory device of claim 1 , wherein the controller is further configured to attach a time stamp indicating a time of arrival for each of the at least two commands at the memory device prior to ordering the at least two commands.
6. The memory device of claim 1 , wherein the ordering of the at least two commands accounts for a time of arrival for each of the commands.
7. The memory device of claim 1 , wherein the reordering accounts for a bit error rate.
8. The memory device of claim 1 , wherein the reordering accounts for die utilization.
9. The memory device of claim 1 , wherein the reordering accounts for a type of memory zone in which data is stored.
10. The memory device of claim 1 , wherein the reordering involves a command arbitration performed by a controller of the memory device.
11. The memory device of claim 10 , wherein the command arbitration is performed in a weighted round robin algorithm.
12. The memory device of claim 11 , wherein weights used for the weighted round robin algorithm are assigned to the at least two commands by the host.
13. The memory device claim 12 , wherein the weights used are an administrative category, an urgent category, a high priority category, a medium priority category and a low priority category.
14. The memory device of claim 1 , wherein the controller is configured to provide a quality of service classification.
15. The memory device of claim 1 , further comprising:
an interface module configured to transmit and receive data from at least one memory array;
a host interface module configured to transmit and receive data from a host;
a time stamp arrangement configured to record a time when a command is received from the host through the host interface module, the time stamp arrangement connected to the host interface module;
a command arbitration arrangement connected to the host interface module, the command arbitration arrangement configured to receive commands received by the host interface module and arbitrate an operational order for the received commands; and
a command queueing arrangement connected to the host interface and the interface module, wherein the command queueing arrangement is configured to accept commands placed in an order by the command arbitration arrangement.
16. The memory device of claim 15 , wherein the at least one memory array is a non-volatile memory array.
17. The memory device of claim 16 , wherein the non-volatile memory array is a NAND memory array.
18. The memory device of claim 15 , further comprising an error correction module.
19. The memory device of claim 18 , further comprising a command scheduler coupled to the command queueing arrangement.
20. The memory device of claim 19 , further comprising a completion queue manager.