Circuit to reduce gating overall system performance
Aspects of a storage device are provided that reduce calculations for identifying physical locations of data during a read operation. In one aspect, a memory device includes one or more memory arrays. Each array includes multiple chunks of memory. The device includes a first set of registers for storing prefixed starting addresses for each array. The device further includes control logic that may identify bad physical address in each array. For each successive chunk in each array and based on the prefixed starting address and the bad physical address locations, the device may determine a pointer to a starting physical address for the chunk. The pointer may be stored in a second set of registers for use in register read operations.
1. A storage device, comprising:
one or more memory arrays each comprising a plurality of chunks, each chunk comprising a plurality of consecutive memory locations;
first registers configured to store a prefixed starting address for each chunk; and
control logic configured, during a power-on-read (POR) operation, to:
identify bad physical address locations in each array;
determine, for each chunk in an array based on the prefixed starting address and the bad physical address locations, a pointer to a starting physical address; and
store the pointer in second registers for use in register read operations.
2. The device of claim 1 , wherein the control logic is further configured to shift a pointer to a memory location in a chunk based on a number of bad physical addresses in an array that precede the memory location.
3. The device of claim 1 , wherein:
each chunk includes a plurality of redundant memory locations arranged sequentially after the last chunk and configured to replace a bad physical address location in the chunk; and
the pointer to the bad physical address location is shifted to point to a next available one of the redundant memory locations.
4. The device of claim 1 , wherein the memory locations comprise memory cells arranged on a substrate in columns, and the addresses comprise column addresses.
5. The device of claim 1 , wherein the control logic is further configured to:
receive a register read instruction and a logical address from a storage controller; and
retrieve the requested data from latch circuits in the memory array using the corresponding prefixed starting address and corresponding stored pointer.
6. The device of claim 5 , wherein the latch circuits comprise X-data latch (XDL) circuits.
7. The die of claim 5 , further comprising a second multiplexer coupled to an output of the second registers and configured to select a stored pointer corresponding to an address included with a register read.
8. The device of claim 1 , further comprising a first multiplexer configured to select one of the pre-fixed starting addresses based on the identified address information received in a register read operation.
9. The device of claim 8 , further comprising a second multiplexer configured to select one of the stored pointer values from the second registers for use with the selected pre-fixed starting address to determine a physical location of data based on address information received in a register read operation.
10. The device of claim 9 , further comprising:
a third multiplexer coupled to an output of the first multiplexer and a logical address input; and
a fourth multiplexer coupled to an output of the second multiplexer and an output of the control logic, the third and fourth multiplexers being configured to provide backward compatibility for calculating a pointer during a pending register read operation.
11. The device of claim 1 , wherein
the array comprises a memory plane, and
each of the prefixed starting addresses are shared for use with each of the planes.
12. The device of claim 1 , wherein each of the prefixed starting addresses includes an allocated number of bits for error correction code (ECC).
13. The device of claim 1 , wherein each of the consecutive memory locations comprises a plurality of dedicated redundancy memory locations at an end for use in lieu of the bad physical address locations.
14. The die of claim 1 , further comprising a first multiplexer coupled to an output of the first registers and configured to select one of the initial column addresses.
15. The die of claim 1 , wherein each of the memory chunks is allocated additional bits for error correction code (ECC).
16. A storage device, comprising:
one or more memory planes each partitioned into consecutive chunks, each chunk arranged as sequential columns of memory cells having a starting address stored in first registers; and
control logic configured, during a power-on-read (POR) operation, to:
identify information comprising bad physical addresses in each plane;
determine, for each chunk in each plane based on the corresponding starting address and the bad physical address information, a pointer to a memory location; and
store the pointers in second registers for use with the starting addresses in performing register reads.
17. The device of claim 16 , wherein the control logic is further configured to determine the pointer for at least some of the chunks by shifting a value of the pointer by an amount corresponding to a number of bad physical addresses preceding a starting address of the at least some of the chunks.
18. The device of claim 16 , wherein the memory cells comprise one of NAND flash or NOR flash memory.
19. The device of claim 16 , wherein each of the chunks is allocated a preconfigured number of physical memory locations for use as error correction code (ECC).
20. A storage device, comprising:
a plurality of consecutive memory chunks each arranged as columns of memory cells;
first registers configured to store an initial column address for each chunk; and
control logic configured, during a power-on-read (POR) operation, to:
identify bad physical addresses in each chunk;
retrieve, from the first registers for each successive chunk, the starting column address;
determine a pointer to a memory location for the initial column address for each block, wherein at least some of the pointers are shifted based on the bad physical addresses; and
store the pointers in second registers for use in register read operations.