Advanced CE encoding for bus multiplexer grid for SSD
The present disclosure generally relates to a method and device for accessing more dies per channel in a data storage device. Each flash interface module (FIM) can have any number of bus multiplexers coupled thereto, and each bus multiplexer can have any number of memory devices coupled thereto. The bus multiplexers can be connected in series or in parallel to the FIM. The individual bus multiplexers can be addressed by a chip enable (CE) command that identifies the specific bus multiplexer as well as the specific memory device of the specific bus multiplexer. The information in the CE command allows more dies per channel without creating signal interference (SI) or limiting transmission performance.
1. A data storage device, comprising:
a plurality of memory devices;
a plurality of bus multiplexers, wherein each bus multiplexer is coupled to one or more memory devices of the plurality of memory devices;
a flash interface module coupled to the plurality of bus multiplexers; and
a controller coupled to the flash interface module, wherein the controller is configured to:
send a chip enable command through the flash interface module, wherein:
the chip enable command includes a bus multiplexer identifier and a memory device identifier;
the chip enable command comprises a ASIC_CE signal, a ASIC_CLE signal, and a ASIC_ALE signal for identifying a bus multiplexer of the plurality of bus multiplexers and a memory device of the plurality of memory devices;
the ASIC_CE signal has a high portion and a low portion;
the ASIC_ALE signal has a high portion and a low portion;
the ASIC_CLE signal has a high portion and a low portion;
the ASIC_ALE signal is the low portion when the ASIC_CE signal is the low portion and the ASIC_CLE signal is the high portion when identifying the bus multiplexer of the plurality of bus multiplexers and the memory device of the plurality of memory devices; and
the chip enable command is within a larger command, wherein:
the larger command comprises a prefix portion and either a read command or a write command; and
the chip enable command is between the prefix portion and the read or write command.
2. The data storage device of claim 1 , wherein each bus multiplexer is configured to ignore a chip enabled command directed to a different bus multiplexer.
3. The data storage device of claim 1 , wherein each bus multiplexer is configured to direct a chip enabled command to a specific memory device coupled thereto.
4. The data storage device of claim 1 , wherein the controller is configured to send the chip enable command as part of the larger command that includes the read or the write command.
5. The data storage device of claim 4 , wherein the chip enable command comprises 8 bits.
6. The data storage device of claim 1 , wherein the flash interface module is a first flash interface module, wherein the data storage device includes a plurality of flash interface modules, and wherein each flash interface module of the plurality of flash interface modules is coupled to the plurality of bus multiplexers.
7. The data storage device of claim 1 , wherein the chip enable command is sent with a bus multiplexer signal and a memory device signal.
8. A data storage device, comprising:
a controller;
a plurality of flash interface modules coupled to the controller;
a plurality of bus multiplexers coupled to at least a first flash interface module of the plurality of flash interface modules; and
a plurality of memory devices coupled to a first bus multiplexer of the plurality of bus multiplexers, wherein the controller is configured to:
send a chip enable command to the first flash interface, wherein sending the chip enable command comprises:
sending a first signal to the first flash interface module; and
sending a second signal to the first flash interface module, wherein the second signal is received after the first signal, and wherein the first signal identifies a bus multiplexer of the plurality of bus multiplexers and the second signal identifies a memory device of the plurality of memory devices; and
send a command signal to the first flash interface module, wherein:
the first signal, second signal, and command signals are distinct,
the chip enable command comprises a ASIC_CE signal, a ASIC_CLE signal, and a ASIC_ALE signal for identifying a bus multiplexer of the plurality of bus multiplexers and a memory device of the plurality of memory devices,
the ASIC_CE signal has a high portion and a low portion,
the ASIC_ALE signal has a high portion and a low portion,
the ASIC_CLE signal has a high portion and a low portion,
the ASIC_ALE signal is the low portion when the ASIC_CE signal is the low portion and the ASIC_CLE signal is the high portion when identifying the bus multiplexer of the plurality of bus multiplexers and the memory device of the plurality of memory devices; and
the chip enable command is within a larger command, wherein:
the larger command comprises a prefix portion and the command signal; and
the chip enable command is between the prefix portion and the command signal.
9. The data storage device of claim 8 , wherein the high portion of the ASIC_CE signal identifies the first bus multiplexer.
10. The data storage device of claim 9 , wherein the low portion of the ASIC_CE signal identifies the first memory device.
11. The data storage device of claim 8 , wherein the plurality of bus multiplexers are connected in parallel to the first flash interface module.
12. The data storage device of claim 8 , wherein the plurality of bus multiplexers are connected in series to the first flash interface module.
13. The data storage device of claim 12 , wherein the plurality of bus multiplexers other than the first bus multiplexer are configured to ignore the high portion of the ASIC_CE signal, the low portion of the ASIC_CE signal, and the command signal.
14. The data storage device of claim 8 , wherein each bus multiplexer has a unique ID number that is static or given upon discovery by the controller.
15. A data storage device, comprising:
a plurality of memory devices;
a plurality of bus multiplexers, wherein each bus multiplexer is coupled to at least one memory device of the plurality of memory devices;
a flash interface module coupled to the plurality of bus multiplexers; and
means to deliver a chip enable command signal to a first memory device of the plurality of memory devices, wherein:
the chip enable command comprises a ASIC_CE signal, a ASIC_CLE signal, and a ASIC_ALE signal corresponding to a bus multiplexer of the plurality of bus multiplexers and a memory device of the plurality of memory devices;
the ASIC_CE signal has a high portion and a low portion; the ASIC_ALE signal has a high portion and a low portion; the ASIC_CLE signal has a high portion and a low portion; the ASIC_ALE signal is the low portion when the ASIC_CE signal is the low portion and the ASIC_CLE signal is the high portion when identifying the bus multiplexer of the plurality of bus multiplexers and the memory device of the plurality of memory devices; and
the chip enable command is within a larger command, wherein:
the larger command comprises a prefix portion and either a read command or a write command; and
the chip enable command is between the prefix portion and the read or write command.
16. The data storage device of claim 15 , further comprising means to deliver two distinct signals to the flash interface module.
17. The data storage device of claim 16 , wherein the two distinct signals are different voltages.
18. The data storage device of claim 15 , wherein the flash interface module further comprises means to ignore the chip enable command.
19. The data storage device of claim 15 , further comprising means to permit the chip enable command to pass through the bus multiplexer of the plurality of bus multiplexers.