CPU error remediation during erasure code encoding
Technology that detects computation errors is disclosed, in which a system may include one or more processors and storage logic. The storage logic may be executed by the one or more processors to perform operations comprising: receiving a data vector, the data vector including a plurality of ordered blocks; transposing the data vector into a set of sub vectors, each of the sub vectors including a corresponding data element from each of the ordered blocks; generating a set of discrete cyclic redundancy checks (CRCs) based on the set of sub vectors; transposing the set of discrete CRCs into a set of mixed CRCs, each of the mixed CRCs including a CRC data element from each of the discrete CRCs; and compacting the set of mixed CRCs into a reduced CRC.
1. A system comprising:
one or more processors; and
storage logic that, when executed by the one or more processors, performs operations comprising:
receiving a data vector, the data vector including a plurality of ordered blocks;
transposing the data vector into a set of sub vectors, each of the sub vectors including a corresponding data element from each of the plurality of ordered blocks;
generating a set of discrete cyclic redundancy checks (CRCs) based on the set of sub vectors;
transposing the set of discrete CRCs into a set of mixed CRCs, each of the mixed CRCs including a CRC data element from each of the discrete CRCs; and
compacting the set of mixed CRCs into a reduced CRC.
2. The system of claim 1 , wherein each of the plurality of ordered blocks comprises a data row including sequential data elements.
3. The system of claim 2 , wherein:
transposing the data vector into a set of sub vectors comprises transposing the data row of each ordered block into a data column;
the data column contains the sequential data elements from the data row of the ordered block;
the data column of each of the ordered blocks collectively forms a transposed data matrix;
the transposed data matrix includes a plurality of mixed sequential rows;
each mixed sequential row of the plurality of mixed sequential rows includes a group of ordered data elements at a corresponding tier; and
the group of ordered data elements includes the corresponding data element from each of the ordered blocks at the corresponding tier.
4. The system of claim 1 , wherein:
the set of sub vectors comprises a data matrix including a plurality of sequential rows;
each of the sequential rows includes a set of mixed data elements comprising the corresponding data element from each of the ordered blocks; and
generating the set of discrete CRCs based on the set of sub vectors comprises:
generating a discrete CRC for each sequential row of the sequential rows of the data matrix using the set of mixed data elements from the sequential row.
5. The system of claim 1 , wherein transposing the set of discrete CRCs into a set of mixed CRCs comprises transposing 8 32-bit CRCs to a 32-byte data vector.
6. The system of claim 1 , wherein compacting the set of mixed CRCs into a reduced CRC comprises:
applying a compacting function to the set of mixed CRCs to obtain the reduced CRC, the compacting function comprising a higher degree polynomial.
7. The system of claim 1 , wherein:
the data vector includes an associated precomputed parity; and
the operations further comprise:
generating a parity CRC for the associated precomputed parity;
performing a comparison between the parity CRC and the reduced CRC; and
determining an error in the data vector based on the comparison.
8. A computer-implemented method for detecting computation errors, the computer-implemented method comprising:
receiving a data vector, the data vector including a plurality of ordered blocks;
transposing the data vector into a set of sub vectors, each of the sub vectors including a corresponding data element from each of the ordered blocks;
generating a set of discrete cyclic redundancy checks (CRCs) based on the set of sub vectors;
transposing the set of discrete CRCs into a set of mixed CRCs, each of the mixed CRCs including a CRC data element from each of the discrete CRCs; and
compacting the set of mixed CRCs into a reduced CRC.
9. The computer-implemented method of claim 8 , wherein each of the ordered blocks comprises a data row with a plurality of sequential columns respectively containing sequential data elements.
10. The computer-implemented method of claim 9 , wherein:
transposing the data vector into a set of sub vectors comprises transposing the data row of each ordered block into a data column;
the data column contains the sequential data elements from the data row of the ordered block;
the data column of each of the ordered blocks collectively forms a transposed data matrix;
the transposed data matrix includes a plurality of mixed sequential rows;
each mixed sequential row of the plurality of mixed sequential rows includes a group of ordered data elements at a corresponding tier; and
the group of ordered data elements includes the corresponding data element from each of the ordered blocks at the corresponding tier.
11. The computer-implemented method of claim 8 , wherein:
the set of sub vectors comprises a data matrix including a plurality of sequential rows;
each of the sequential rows includes a set of mixed data elements comprising the corresponding data element from each of the ordered blocks; and
generating the set of discrete CRCs based on the set of sub vectors comprises:
generating a discrete CRC for each sequential row of the sequential rows of the data matrix using the set of mixed data elements from the sequential row.
12. The computer-implemented method of claim 11 , wherein the discrete CRC is a CRC32c.
13. The computer-implemented method of claim 8 , wherein transposing the set of discrete CRCs into a set of mixed CRCs comprises transposing 8 32-bit CRCs to a 32-byte data vector.
14. The computer-implemented method of claim 8 , wherein compacting the set of mixed CRCs into a reduced CRC comprises:
applying a compacting function to the set of mixed CRCs to obtain the reduced CRC, the compacting function comprising a higher degree polynomial.
15. The computer-implemented method of claim 8 , wherein the data vector includes an associated precomputed parity, and the method further comprises:
generating a parity CRC for the associated precomputed parity.
16. The computer-implemented method of claim 15 , further comprising:
performing a comparison between the parity CRC and the reduced CRC; and
determining an error in the data vector based on the comparison.
17. A system comprising:
one or more processors; and
a storage logic in memory executable by the one or more processors, the storage logic comprising:
means for receiving a data vector, the data vector including a plurality of ordered blocks;
means for transposing the data vector into a set of sub vectors, each of the sub vectors including a corresponding data element from each of the ordered blocks;
means for generating a set of discrete cyclic redundancy checks (CRCs) based on the set of sub vectors;
means for transposing the set of discrete CRCs into a set of mixed CRCs, each of the mixed CRCs including a CRC data element from each of the discrete CRCs; and
means for compacting the set of mixed CRCs into a reduced CRC.
18. The system of claim 1 , wherein the operations further comprise verifying integrity of the data vector using the reduced CRC.
19. The computer-implemented method of claim 8 , further comprising verifying integrity of the data vector using the reduced CRC.
20. The system of claim 17 , wherein the storage logic further comprises means for verifying integrity of the data vector using the reduced CRC.