Hardware accelerator circuits for near storage compute systems
An apparatus is provided that includes a memory system that includes a memory controller coupled to a storage device capable of streaming data at a first data rate. The memory controller is configured to read a first amount of input data from the storage device at an input data rate equals the first data rate, and provide the first amount of input data at the input data rate to a hardware circuit. The hardware circuit is configured to filter the first amount of input data to provide a second amount of output data at an output data rate, the second amount of output data less than the first amount of input data, the output data rate less than the input data rate. The hardware circuit filters the first amount of input data without repeatedly moving data back and forth between the storage device, a memory buffer, and the hardware circuit.
1. An apparatus comprising:
a memory system comprising:
a non-volatile storage device configured to stream data at a first data rate;
a memory controller coupled to the non-volatile storage device; and
a hardware circuit coupled to the memory controller,
wherein:
the memory controller is configured to:
read a first amount of input data from the non-volatile storage device at an input data rate that equals the first data rate; and
provide the first amount of input data at the input data rate to the hardware circuit;
the hardware circuit is configured to filter the first amount of input data to provide a second amount of output data at an output data rate, the second amount of output data less than the first amount of input data, the output data rate less than the input data rate; and
the hardware circuit filters the first amount of input data without repeatedly moving data back and forth between the non-volatile storage device, a memory buffer, and the hardware circuit.
2. The apparatus of claim 1 , wherein:
the memory controller is further configured to receive a filter parameter from a host device; and
the hardware circuit is further configured to filter the first amount of input data in accordance with the filter parameter.
3. The apparatus of claim 1 , wherein the hardware circuit is further configured to:
perform a first filter operation on the first amount of input data to provide first filtered data at the input data rate; and
perform a second filter operation on the first filtered data to provide second filtered data at a second data rate less than the input data rate.
4. The apparatus of claim 3 , wherein the hardware circuit is further configured to perform a third filter operation on the second filtered data to provide third filtered data at a third data rate less than the second data rate.
5. The apparatus of claim 3 , wherein the third filtered data comprises the output data.
6. The apparatus of claim 1 , wherein the hardware circuit comprises a plurality of filtering circuits that collectively filter the first amount of input data to provide the second amount of output data at the output data rate.
7. The apparatus of claim 1 , wherein the hardware circuit comprises:
a first filter circuit configured to filter the first amount of input data to provide a first amount of first filtered data less than the first amount of input data; and
a second filter circuit configured to filter the first amount of first filtered data to provide a second amount of second filtered data less than the first amount of first filtered data.
8. The apparatus of claim 1 , wherein the hardware circuit further comprises a third filter circuit configured to filter the second amount of second filtered data to provide a third amount of third filtered data less than the second amount of second filtered data.
9. The apparatus of claim 1 , wherein the third filtered data comprises the output data.
10. The apparatus of claim 1 , wherein the memory system further comprises a data processor circuit configured to:
receive the second amount of output data from the hardware circuit; and
further process the received output data to provide a search result to a host device.
11. The apparatus of claim 1 , wherein the first data rate is greater than or equal to 5 GB/s.
12. A memory system comprising:
a memory controller configured to read a first amount of input data from a non-volatile storage device at a first data rate;
a hardware accelerator circuit that is coupled to the memory controller and that comprises:
a first filter circuit configured to receive at the first data rate the first amount of input data and implement a first filter operation on the received input data to provide a second amount of first filtered data less than the first amount of input data;
a second filter circuit configured to receive at a second data rate less than the first data rate the second amount of first filtered data and implement a second filter operation on the received first filtered data to provide a third amount of second filtered data less than the second amount of first filtered data; and
a third filter circuit configured to receive at a third data rate less than the second data rate the third amount of second filtered data and implement a third filter operation on the received second filtered data to provide a fourth amount of third filtered data less than the third amount of second filtered data,
wherein the first data rate is a rate at which the non-volatile storage device is configured to stream data.
13. The memory system of claim 12 , wherein the input data comprises a database file comprising a plurality of input columns comprising input content, and the first filter operation includes receiving a first filtering criteria that specifies desired input column numbers that specify input columns whose input content is to be selected and provided as the first filtered content.
14. The memory system of claim 13 , wherein the second filter operation includes receiving a second filtering criteria that specifies first filtered content to be selected and provided as the second filtered content.
15. The memory system of claim 14 , wherein the third filter operation includes receiving a third filtering criteria that specifies second filtered content to be selected and provided as the third filtered content.
16. The memory system of claim 12 , wherein the hardware accelerator circuit is further configured to provide the fourth amount of third filtered data as a search result to a host device.
17. The memory system of claim 12 , further comprising a data processor circuit configured to receive the fourth amount of third filtered data, further process the received third filtered data, and provide the further processed data as a search result to a host device.
18. The memory system of claim 12 , wherein the first data rate is greater than or equal to 5 GB/s.
19. A hardware accelerator circuit for a near storage compute system comprising:
a column filter circuit configured to receive an input byte stream from a non-volatile storage device, the input byte stream comprising a first amount of input data comprising input columns of input content, select only input content from desired input columns, and provide the selected input content as a second amount of first filtered columns of first filtered content;
a row filter circuit configured to receive the second amount of first filtered columns of first filtered content from the column filter circuit, search a specified first filtered column to identify any first filtered content that matches a specified first match value, and for each identified match select first filtered content from first filtered columns associated with the specified first filtered column, and provide the selected first filtered content as a third amount of second filtered columns of second filtered content; and
a data filter circuit configured to receive the third amount of second filtered columns of second filtered content from the row filter circuit, search a specified second filtered column to identify any second filtered content that matches a specified second match value, and for each identified match select second filtered content from second filtered columns associated with the specified second filtered column, and provide the selected second filtered content as a fourth amount of third filtered columns of third filtered content,
wherein the column filter circuit operates at a first data rate, the row filter circuit operates at a second data rate less than the first data rate, and the data filter circuit operates at a third data rate less than the second data rate.