Multi-fetching data for multi-pass programming within storage devices
Storage devices include a memory array comprised of a plurality of memory devices. As memory array density increases, multi-pass programming is utilized to reduce negative effects to neighboring memory devices. The use of multi-pass programming requires longer access to the data being programmed. To avoid adding additional lower density or controller memory, data within a host memory is accessed multiple times as needed to provide pieces of data to the memory array, which is configured to comply with the utilized multi-pass programming method. The expected order of the multi-pass programming method can be determined to generate one or more memory pipeline instruction processing queues to direct the components of the storage device memory pipeline to access, re-access, and process the host data in a specific order necessary for delivery to the memory array to comply with the utilized multi-pass programming method.
1. A device comprising:
a processor;
a memory array comprising:
a plurality of memory devices configured to be programmed with a multi-pass programming method; and
a multi-fetch queue logic configured to:
receive a command to write host data to the memory array;
initially access a first piece of data from a host computing device;
process the first piece of data within a memory pipeline prior to programming within the memory array;
subsequently access a second piece of data from the host computing device;
process the second piece of data within the memory pipeline;
utilize the processed first piece of data within the memory pipeline for a first programming pass of one or more memory devices within the memory array;
intermediately store the processed first piece of data in one or more latches communicatively coupled to the plurality of memory devices, wherein the one or more latches are located outside the plurality of memory devices, and wherein if the one or more latches do not have space, the multi-fetch queue logic is configured to present the processed first piece of data to the memory array twice;
utilize the processed second piece of data within the memory pipeline for the first programming pass of the one or more memory devices within the memory array;
re-access the first piece of data within the host computing device;
process the re-accessed first piece of data within the memory pipeline; and
utilize the re-accessed first piece of data to perform a second programming pass of the one or more memory devices within the memory array;
wherein processing the first piece of data comprises:
encrypting the first piece of data and temporarily storing the encrypted first piece of data in a first buffer memory; and
encoding the encrypted first piece of data and temporarily storing the encrypted and encoded first piece of data in a second buffer memory; and
wherein processing the second piece of data comprises:
encrypting the second piece of data and temporarily storing the encrypted second piece of data in the first buffer memory; and
encoding the encrypted second piece of data and temporarily storing the encrypted and encoded second piece of data in the second buffer memory.
2. The device of claim 1 , wherein the multi-pass programming method is a two pass programming method.
3. The device of claim 2 , wherein the two pass programming method is a foggy-fine programming method.
4. The device of claim 1 , wherein the pieces of data are accessed through a host direct memory access (DMA) process.
5. The device of claim 1 , wherein the processing of data within the memory pipeline is based on a memory pipeline instruction processing queue.
6. The device of claim 5 , wherein an order of accessing the data is directed by one or more instructions within memory pipeline instruction processing queue.
7. The device of claim 6 , wherein a determination of the order of data access within the memory pipeline instruction processing queue is generated by the multi-fetch queue logic.
8. The device of claim 1 , wherein any number of subsequent pieces of data may be accessed prior to subsequently accessing the first piece of data.
9. A device comprising:
a processor;
a memory array comprising:
a plurality of memory devices; and
a multi-fetch queue logic configured to:
receive a command to write host data to the memory array;
determine a programming order of the memory array;
produce a pipeline processing instruction queue and a plurality of programming instructions based on the determined programming order of the memory array, wherein the programming order of the memory array requires at least two passes of programming;
access the host data based on the pipeline processing instruction queue, wherein the host data is accessed at least two times;
process, through a data pipeline, the accessed host data based on the pipeline processing instruction queue;
intermediately store the processed host data in one or more latches communicatively coupled to the plurality of memory devices, wherein the one or more latches are located outside the plurality of memory devices, and wherein if the one or more latches do not have space, the multi-fetch queue logic is configured to present the processed host data to the memory array twice;
present the processed host data and the plurality of programming instructions to a memory array interface; and
write the processed host data to the memory array in an order indicated by the programming instructions;
wherein processing the host data comprises:
encrypting the host data and temporarily storing the encrypted host data in a first buffer memory in the data pipeline; and
encoding the encrypted host data and temporarily storing the encrypted and encoded host data in a second buffer memory in the data pipeline.
10. The device of claim 9 , wherein the programming of data within the memory array is a foggy-fine programming method.
11. The device of claim 10 , wherein the programming instructions include foggy-fine programming instructions for specific parts of the data within the host data.
12. The device of claim 9 , wherein the memory array is a quad level cell (QLC) memory array.
13. The device of claim 9 , wherein processing the processed host data through the data pipeline includes encrypting the processed host data.
14. The device of claim 9 , wherein processing the processed host data through the data pipeline includes encoding the processed host data with error correction data.
15. The device of claim 9 , wherein processing the processed host data through the data pipeline includes processing the data through one or more memory array interfaces.
16. A method of writing data to a storage device, comprising:
receiving a command to write host data to the memory array;
determining a multi-pass programming order of the memory array;
producing one or more pipeline processing instruction queues and a plurality of programming instructions based on the determined programming order of the memory array;
accessing the host data on two or more data buses based on the one or more pipeline instruction processing queues, wherein the host data for each data bus is accessed at least two times;
processing, through a single data pipeline, the accessed host data based one or more on the pipeline processing instruction queues, wherein the processing is scheduled between two or more queues;
intermediately storing the accessed host data in one or more latches communicatively coupled to the plurality of memory devices, wherein the one or more latches are located outside the plurality of memory devices, and wherein if the one or more latches do not have space, the accessed host data are presented to the memory array twice;
presenting the processed host data and the plurality of programming instructions to a memory array interface; and
writing the host data to one or more memory arrays in an order indicated by the programming instructions;
wherein processing the host data comprises:
encrypting the host data and temporarily storing the encrypted host data in a first buffer memory in the single data pipeline; and
encoding the encrypted host data and temporarily storing the encrypted and encoded host data in a second buffer memory in the single data pipeline.
17. The method of claim 16 , wherein the scheduling is handled by a simple scheduler.
18. The method of claim 16 , wherein the two or more data buses correlate to two or more planes of memory dies within the storage device.