Read threshold adjustment using reference data
Apparatuses, systems, and methods are disclosed for read threshold adjustment using reference data for non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to write a predetermined reference data pattern to a region of an array. A controller may be configured to read reference data from a region. A controller may be configured to set one or more read thresholds based on identifying differences between reference data and a predetermined reference data pattern.
1. An apparatus comprising:
an array of non-volatile memory cells; and
a controller configured to:
write a predetermined reference data pattern together with user data to a region of the array;
read reference data from the region;
identify an offset for one or more read thresholds based on a predetermined correspondence between offsets and errors in the reference data, wherein the predetermined correspondence is based on a characterization of the array;
shift the one or more read thresholds by the offset and
use the one or more read thresholds shifted by the offset to read the user data.
2. The apparatus of claim 1 , wherein the errors in the reference data comprise changes from bits associated with an erased state for the cells and from bits associated with a highest state for the cells.
3. The apparatus of claim 2 , wherein the erased state is associated with lower page bits and the highest state is associated with upper page bits.
4. The apparatus of claim 1 , wherein the predetermined reference data pattern is associated with a plurality of pages stored by cells coupled to a word line.
5. The apparatus of claim 1 , wherein a size of the region storing the predetermined reference data pattern increases as the array ages.
6. The apparatus of claim 1 , wherein the reference data is compared to the predetermined reference data pattern in response to a comparison by the controller of a failed bit count against an error threshold.
7. The apparatus of claim 6 , wherein, in response to a comparison with the error threshold, wherein the controller determines that a failed bit count exceeds the error threshold or that there are uncorrectable errors, the controller calculates the offset for the one or more read thresholds based on the reference data.
8. The apparatus of claim 7 , wherein the controller is configured to further shift the one or more read thresholds by a second offset that is smaller than the offset and compensates for read fluctuations.
9. The apparatus of claim 8 , wherein the second offset is variable.
10. The apparatus of claim 8 , wherein the controller recursively calculates the second offset, increments a loop count, and applies the second offset to the one or more read thresholds until the failed bit count satisfies the error threshold or the loop count exceeds a loop count threshold.
11. A method comprising:
acquiring a current state of a test pattern in an array of non-volatile memory;
identifying differences between the current state and a previous state for the test pattern;
adjusting read thresholds for a portion of the array of non-volatile memory associated with the test pattern based on a predetermined correspondence between read threshold adjustments and the identified differences, wherein the predetermined correspondence is based on a characterization ofthe array; and
using the adjusted read thresholds to read user data stored with the test pattern in the array.
12. The method of claim 11 , wherein acquiring the current state of the test pattern comprises:
applying an error correction code to data stored in the array of non-volatile memory; and
acquiring the current state based on the application of the error correction code.
13. The method of claim 11 , wherein adjusting read thresholds comprises shifting the read thresholds by an offset based on the test pattern.
14. The method of claim 13 , wherein adjusting the read threshold comprises shifting the read thresholds by a second offset that is smaller than the offset and compensates for read fluctuations.
15. The method of claim 14 , further comprising:
recursively calculating the second offset;
incrementing a loop count; and
applying the second offset to the read thresholds until a failed bit count satisfies an error threshold or the loop count exceeds a loop count threshold.
16. An apparatus comprising:
means for reading at least one cell of a non-volatile memory array;
means for identifying errors associated with at least an erase state and a highest state of a plurality of data states; and
means for adjusting read thresholds based on the identified errors by shifting the read threshold by an offset, the offset based on a predetermined correspondence between offsets and identified errors, wherein the predetermined correspondence is based on a characterization of the array, and the adjusted read thresholds are used to read user data.
17. The apparatus of claim 16 , wherein the means for identifying errors is configured to read a test pattern stored in the at least one cell associated with the plurality of data states, wherein the errors are data states not associated with one of the erase state and the highest state.