IP Library Granted Patent US 11,907,583
Granted Patent B2
US 11,907,583 · App. 17/834,840 · Granted Feb 20, 2024

Multiple sets of trim parameters

Inventors: Tomer Tzvi Eliash (Kfar Saba, IL); Asaf Gueta (Or Yehuda, IL); Inon Cohen (Oranit, IL); Yuval Grossman (Kiryat Ono, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0659G06F3/0604G06F3/0679G06F13/1668
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Quick Facts
Patent No.
US 11,907,583
App. No.
17/834,840
Granted
Feb 20, 2024
Kind
B2
Abstract

Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Claims (46)

1. A computer-implemented method, comprising:

in response to a determination that a value of an operating condition of a first non-volatile memory device satisfies a certain first threshold, causing transfer of one or more first control signals to cause one or more first selected trim sets to be transferred from a first register to a second register to allow the one or more first selected trim sets to be used by the first non-volatile memory device, wherein the one or more first selected trim sets are associated with the satisfaction of the certain first threshold for an operating configuration of the first non-volatile memory device;

configuring a multiplexer of the first non-volatile memory device with an order configuration, ordering a plurality of trim sets stored in the first register to be transferred from the first register to the second register in a transfer sequence;

selecting the one or more first selected trim sets from the plurality of trim sets; and

transferring, the one or more first selected trim sets in the transfer sequence, according to the order configuration configured in the multiplexer, from the first register to the second register.

2. The computer-implemented method of claim 1 , wherein the value of the operating condition of the first non-volatile memory device is a temperature data of the first non-volatile memory device.

3. The computer-implemented method of claim 1 , wherein the value of the operating condition of the first non-volatile memory device is a program erase cycles (PEC) data of the first non-volatile memory device.

4. The computer-implemented method of claim 1 , wherein selecting the one or more first selected trim sets from the plurality of trim sets comprises:

selecting one or more input/output lines communicatively coupled to the one or more first selected trim sets respectively, wherein the one or more input/output lines are from a plurality of input/output lines coupled between the first register and the multiplexer.

5. The computer-implemented method of claim 1 , comprising:

determining whether a value of an operating condition of a second non-volatile memory device satisfies a certain second threshold; and

in response to determining that the value of the operating condition of the second non-volatile memory device satisfies the certain second threshold:

identifying one or more second selected trim sets calibrated for the second non-volatile memory device and associated with the satisfaction of the certain second threshold for an operating configuration of the second non-volatile memory device; and

transferring one or more second control signals for the one or more second selected trim sets to the second non-volatile memory device, causing the one or more second selected trim sets to be used by the second non-volatile memory device.

6. The computer-implemented method of claim 5 , wherein the one or more second selected trim sets are different from the one or more first selected trim sets.

7. The computer-implemented method of claim 5 , wherein the one or more first selected trim sets are associated with quad-level cell programming of the first non-volatile memory device, and the one or more second selected trim sets are associated with triple-level cell programming of the second non-volatile memory device.

8. The computer-implemented method of claim 1 , wherein the one or more first selected trim sets are calibrated based on a manufacturing variance of the first non-volatile memory device.

9. The computer-implemented method of claim 1 , wherein the determination that the value of the operating condition of the first non-volatile memory device satisfies a certain first threshold is triggered by a new or changed value of the operating condition.

10. The computer-implemented method of claim 1 , wherein the first register is configured with multiple input/output interfaces, and each of a plurality of input/output lines is communicatively coupled to one of the multiple input/output interfaces.

11. A data storage system, comprising:

a first non-volatile memory device, comprising:

a first register configured to store a plurality of trim sets;

a second register; and

a multiplexer coupled between the first register and the second register; and

a controller configured to cause:

in response to a determination that a value of an operating condition of the first non-volatile memory device satisfies a certain first threshold, transfer of one or more first control signals to cause one or more first selected trim sets to be transferred from the first register to the second register to allow the one or more first selected trim sets to be used by the first non-volatile memory device, wherein the one or more first selected trim sets are associated with the satisfaction of the certain first threshold for an operating configuration of the first non-volatile memory device;

wherein:

the multiplexer is configured with an order configuration, ordering the plurality of trim sets stored in the first register to be transferred from the first register to the second register in a transfer sequence;

when the multiplexer selects the one or more first selected trim sets from the plurality of trim sets, the multiplexer is configured, according to the order configuration, to transfer, the one or more first selected trim sets in the transfer sequence from the first register to the second register.

12. The data storage system of claim 11 , wherein the value of the operating condition of the first non-volatile memory device is a temperature data of the first non-volatile memory device.

13. The data storage system of claim 11 , wherein the value of the operating condition of the first non-volatile memory device is a program erase cycles (PEC) data of the first non-volatile memory device.

14. The data storage system of claim 11 , wherein the one or more first selected trim sets are communicatively coupled to one or more input/output lines respectively, wherein the one or more input/output lines are from a plurality of input/output lines coupled between the first register and the multiplexer.

15. The data storage system of claim 11 , wherein the controller is configured to cause:

determining whether a value of an operating condition of a second non-volatile memory device satisfies a certain second threshold; and

in response to determining that the value of the operating condition of the second non-volatile memory device satisfies the certain second threshold:

identifying one or more second selected trim sets calibrated for the second non-volatile memory device and associated with the satisfaction of the certain second threshold for an operating configuration of the second non-volatile memory device; and

transferring one or more second control signals for the one or more second selected trim sets to the second non-volatile memory device, causing the one or more second selected trim sets to be used by the second non-volatile memory device.

16. The data storage system of claim 11 , wherein the one or more first selected trim sets are calibrated based on a manufacturing variance of the first non-volatile memory device.

17. The data storage system of claim 11 , wherein the determination that the value of the operating condition of the first non-volatile memory device satisfies a certain first threshold is triggered by a new or changed value of the operating condition.

18. An apparatus, comprising:

means for, in response to a determination that a value of an operating condition of a first non-volatile memory device satisfies a certain first threshold, causing transfer of one or more first control signals to cause one or more first selected trim sets to be transferred from a first register to a second register to allow the one or more first selected trim sets to be used by the first non-volatile memory device, wherein the one or more first selected trim sets are associated with the satisfaction of the certain first threshold for an operating configuration of the first non-volatile memory device;

means for configuring a multiplexer of the first non-volatile memory device with an order configuration, ordering a plurality of trim sets stored in the first register to be transferred from the first register to the second register in a transfer sequence;

means for selecting the one or more first selected trim sets from the plurality of trim sets; and

means for transferring, the one or more first selected trim sets in the transfer sequence, according to the order configuration configured in the multiplexer, from the first register to the second register.

19. The apparatus of claim 18 , wherein the determination that the value of the operating condition of the first non-volatile memory device satisfies a certain first threshold is triggered by a new or changed value of the operating condition.

20. The apparatus of claim 18 , wherein the value of the operating condition of the first non-volatile memory device is a program erase cycles data of the first non-volatile memory device.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2022
From: ELIASH, TOMER TZVI; GUETA, ASAF; COHEN, INON; GROSSMAN, YUVAL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060667/0153 →